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uzzzer

Quartus: Проблема с компиляцией "work".

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Добрый вечер !

Помогите, пожалуйста с компиляцией проекта, компилятор ругается:

Spoiler

Error (10481): VHDL Use Clause error at ip_16z091_01_top.vhd(865): design library "work" does not contain primary unit "Hard_IP_x4". Verify that the primary unit exists in the library and has been successfully compiled.

Удалил из проекта все файлы, добавил заново, но ошибка повторяется. Согласно readme все должно работать. 

файл проекта: \PCIe2VME\Synthesis\A25_top.qpf

PCIe2VME.zip

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19 hours ago, uzzzer said:

а: \PCIe2VME\Synthesis\A25_top.qpf

наверное qsf
Требует корку для pcie, но как то ее по путям нет. Возможно ее нужно загенерить самому из соответствующего tcl

 

Вобще вроде qsf написан так, что вроде само все нагенерится, может ему помочь и руками создать

Edited by new123

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10 minutes ago, new123 said:

 

наверное qsf
Требует корку для pcie, но как то ее по путям нет. Возможно ее нужно загенерить самому из соответствующего tcl

 

Вобще вроде qsf написан так, что вроде само все нагенерится, может ему помочь и руками создать

 

А как это сделать? Извиняюсь, может глупый вопрос...

Вот еще, собственно и код на который ругается Квартус:

Spoiler

COMPONENT Hard_IP_x4 is 
        port (
              -- inputs:
                 signal app_int_sts : IN STD_LOGIC;
                 signal app_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal app_msi_req : IN STD_LOGIC;
                 signal app_msi_tc : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal busy_altgxb_reconfig : IN STD_LOGIC;
                 signal cal_blk_clk : IN STD_LOGIC;
                 signal cpl_err : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
                 signal cpl_pending : IN STD_LOGIC;
                 signal crst : IN STD_LOGIC;
                 signal fixedclk_serdes : IN STD_LOGIC;
                 signal gxb_powerdown : IN STD_LOGIC;
                 signal hpg_ctrler : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal lmi_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
                 signal lmi_din : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal lmi_rden : IN STD_LOGIC;
                 signal lmi_wren : IN STD_LOGIC;
                 signal npor : IN STD_LOGIC;
                 signal pclk_in : IN STD_LOGIC;
                 signal pex_msi_num : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal phystatus_ext : IN STD_LOGIC;
                 signal pipe_mode : IN STD_LOGIC;
                 signal pld_clk : IN STD_LOGIC;
                 signal pll_powerdown : IN STD_LOGIC;
                 signal pm_auxpwr : IN STD_LOGIC;
                 signal pm_data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
                 signal pm_event : IN STD_LOGIC;
                 signal pme_to_cr : IN STD_LOGIC;
                 signal reconfig_clk : IN STD_LOGIC;
                 signal reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal refclk : IN STD_LOGIC;
                 signal rx_in0 : IN STD_LOGIC;
                 signal rx_in1 : IN STD_LOGIC;
                 signal rx_in2 : IN STD_LOGIC;
                 signal rx_in3 : IN STD_LOGIC;
                 signal rx_st_mask0 : IN STD_LOGIC;
                 signal rx_st_ready0 : IN STD_LOGIC;
                 signal rxdata0_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rxdata1_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rxdata2_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rxdata3_ext : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rxdatak0_ext : IN STD_LOGIC;
                 signal rxdatak1_ext : IN STD_LOGIC;
                 signal rxdatak2_ext : IN STD_LOGIC;
                 signal rxdatak3_ext : IN STD_LOGIC;
                 signal rxelecidle0_ext : IN STD_LOGIC;
                 signal rxelecidle1_ext : IN STD_LOGIC;
                 signal rxelecidle2_ext : IN STD_LOGIC;
                 signal rxelecidle3_ext : IN STD_LOGIC;
                 signal rxstatus0_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal rxstatus1_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal rxstatus2_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal rxstatus3_ext : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal rxvalid0_ext : IN STD_LOGIC;
                 signal rxvalid1_ext : IN STD_LOGIC;
                 signal rxvalid2_ext : IN STD_LOGIC;
                 signal rxvalid3_ext : IN STD_LOGIC;
                 signal srst : IN STD_LOGIC;
                 signal test_in : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
                 signal tx_st_data0 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
                 signal tx_st_eop0 : IN STD_LOGIC;
                 signal tx_st_err0 : IN STD_LOGIC;
                 signal tx_st_sop0 : IN STD_LOGIC;
                 signal tx_st_valid0 : IN STD_LOGIC;

              -- outputs:
                 signal app_int_ack : OUT STD_LOGIC;
                 signal app_msi_ack : OUT STD_LOGIC;
                 signal clk250_out : OUT STD_LOGIC;
                 signal clk500_out : OUT STD_LOGIC;
                 signal core_clk_out : OUT STD_LOGIC;
                 signal derr_cor_ext_rcv0 : OUT STD_LOGIC;
                 signal derr_cor_ext_rpl : OUT STD_LOGIC;
                 signal derr_rpl : OUT STD_LOGIC;
                 signal dlup_exit : OUT STD_LOGIC;
                 signal hotrst_exit : OUT STD_LOGIC;
                 signal ko_cpl_spc_vc0 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
                 signal l2_exit : OUT STD_LOGIC;
                 signal lane_act : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal lmi_ack : OUT STD_LOGIC;
                 signal lmi_dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal ltssm : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal pme_to_sr : OUT STD_LOGIC;
                 signal powerdown_ext : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal r2c_err0 : OUT STD_LOGIC;
                 signal rate_ext : OUT STD_LOGIC;
                 signal rc_pll_locked : OUT STD_LOGIC;
                 signal rc_rx_digitalreset : OUT STD_LOGIC;
                 signal reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
                 signal reset_status : OUT STD_LOGIC;
                 signal rx_fifo_empty0 : OUT STD_LOGIC;
                 signal rx_fifo_full0 : OUT STD_LOGIC;
                 signal rx_st_bardec0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rx_st_be0 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rx_st_data0 : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
                 signal rx_st_eop0 : OUT STD_LOGIC;
                 signal rx_st_err0 : OUT STD_LOGIC;
                 signal rx_st_sop0 : OUT STD_LOGIC;
                 signal rx_st_valid0 : OUT STD_LOGIC;
                 signal rxpolarity0_ext : OUT STD_LOGIC;
                 signal rxpolarity1_ext : OUT STD_LOGIC;
                 signal rxpolarity2_ext : OUT STD_LOGIC;
                 signal rxpolarity3_ext : OUT STD_LOGIC;
                 signal suc_spd_neg : OUT STD_LOGIC;
                 signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal tl_cfg_ctl_wr : OUT STD_LOGIC;
                 signal tl_cfg_sts : OUT STD_LOGIC_VECTOR (52 DOWNTO 0);
                 signal tl_cfg_sts_wr : OUT STD_LOGIC;
                 signal tx_cred0 : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
                 signal tx_fifo_empty0 : OUT STD_LOGIC;
                 signal tx_fifo_full0 : OUT STD_LOGIC;
                 signal tx_fifo_rdptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal tx_fifo_wrptr0 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal tx_out0 : OUT STD_LOGIC;
                 signal tx_out1 : OUT STD_LOGIC;
                 signal tx_out2 : OUT STD_LOGIC;
                 signal tx_out3 : OUT STD_LOGIC;
                 signal tx_st_ready0 : OUT STD_LOGIC;
                 signal txcompl0_ext : OUT STD_LOGIC;
                 signal txcompl1_ext : OUT STD_LOGIC;
                 signal txcompl2_ext : OUT STD_LOGIC;
                 signal txcompl3_ext : OUT STD_LOGIC;
                 signal txdata0_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal txdata1_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal txdata2_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal txdata3_ext : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal txdatak0_ext : OUT STD_LOGIC;
                 signal txdatak1_ext : OUT STD_LOGIC;
                 signal txdatak2_ext : OUT STD_LOGIC;
                 signal txdatak3_ext : OUT STD_LOGIC;
                 signal txdetectrx_ext : OUT STD_LOGIC;
                 signal txelecidle0_ext : OUT STD_LOGIC;
                 signal txelecidle1_ext : OUT STD_LOGIC;
                 signal txelecidle2_ext : OUT STD_LOGIC;
                 signal txelecidle3_ext : OUT STD_LOGIC
              );
end COMPONENT Hard_IP_x4;

 

Немного напрягает конструкция для компонента:

Spoiler

COMPONENT Hard_IP_x4 is 
        port (
              -- inputs:
                 
  				.......

              -- outputs:
  				.......
              );
end COMPONENT Hard_IP_x4;

 

Разве так можно определять компонент?

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14 hours ago, uzzzer said:

Разве так можно определять компонент?

не силен в vhdl, только verilog, так что именно этот момент не подскажу

Посмотрите внимательно лог компиляции, у вас перед стартом компиляции должен запускаться скрипт генерации корок, согласно qsf
 

set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:gen_ip_cores.tcl"

Как только он стартует, судя по коду, он должен принтануть в лог 

Executing A25 pre-flow script

Ну и далее, идет ли у него какой процесс генерации или нет, все что связано со словом qmegawiz, особенно после фразы
 

Testing for megawizard regeneration in $dir:$files

По результату всего этого, должен появиться qip файл, который автоматически подключается к проекту. В архиве у вас его нет, проект собраться не может

Edited by new123

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Если закоментить строки в gen_ip_cores.tcl:


#source ../16z091-01_src/Source/x4/x4.tcl
#source ../16z091-01_src/Source/x1/x1.tcl

То, компиляция стартует, но потом все равно вылетает с той же ошибкой.

Spoiler

Info: *******************************************************************
Info: Running Quartus Prime Shell
	Info: Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition
	Info: Processing started: Thu Nov 05 11:49:48 2020
Info: Command: quartus_sh -t gen_ip_cores.tcl compile A25_top A25_top
Info: Quartus(args): compile A25_top A25_top
Info: Using INI file D:/FILES/Projects/WORK/ADSTP/DOC/VMEbus/Test/FPGA/PCIe2VME/Synthesis/quartus.ini
Info: Executing A25 pre-flow script
Info: Testing for megawizard regeneration in ../16z091-01_src/Source/alt_reconf: alt_reconf 
Info: Testing for megawizard regeneration in ../Source/pll_pcie: pll_pcie 
Info: Testing for megawizard regeneration in ../16z126-01_src/Source/z126_01_pasmi: z126_01_pasmi_m25p32 
Info: Testing for megawizard regeneration in ../16z126-01_src/Source/z126_01_ru: z126_01_ru_cycloneiv 
Info: A25 pre-flow script execution complete
Info (23030): Evaluation of Tcl script gen_ip_cores.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
	Info: Peak virtual memory: 4492 megabytes
	Info: Processing ended: Thu Nov 05 11:49:48 2020
	Info: Elapsed time: 00:00:00
	Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
	Info: Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition
	Info: Processing started: Thu Nov 05 11:49:49 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A25_top -c A25_top
Info: Using INI file D:/FILES/Projects/WORK/ADSTP/DOC/VMEbus/Test/FPGA/PCIe2VME/Synthesis/quartus.ini
Info (20030): Parallel compilation is enabled and will use 14 of the 14 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/generic_dcfifo_mixedw.vhd
	Info (12022): Found design unit 1: generic_dcfifo_mixedw-syn
	Info (12023): Found entity 1: generic_dcfifo_mixedw
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/z091_01_wb_slave.vhd
	Info (12022): Found design unit 1: z091_01_wb_slave-z091_01_wb_slave_arch
	Info (12023): Found entity 1: z091_01_wb_slave
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/z091_01_wb_master.vhd
	Info (12022): Found design unit 1: z091_01_wb_master-z091_01_wb_master_arch
	Info (12023): Found entity 1: z091_01_wb_master
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/tx_put_data.vhd
	Info (12022): Found design unit 1: tx_put_data-tx_put_data_arch
	Info (12023): Found entity 1: tx_put_data
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/tx_module.vhd
	Info (12022): Found design unit 1: tx_module-tx_module_arch
	Info (12023): Found entity 1: tx_module
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/tx_ctrl.vhd
	Info (12022): Found design unit 1: tx_ctrl-tx_ctrl_arch
	Info (12023): Found entity 1: tx_ctrl
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/tx_compl_timeout.vhd
	Info (12022): Found design unit 1: tx_compl_timeout-tx_compl_timeout_arch
	Info (12023): Found entity 1: tx_compl_timeout
Info (12021): Found 1 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/src_utils_pkg.vhd
	Info (12022): Found design unit 1: src_utils_pkg
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/rx_module.vhd
	Info (12022): Found design unit 1: rx_module-rx_module_arch
	Info (12023): Found entity 1: rx_module
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/rx_len_cntr.vhd
	Info (12022): Found design unit 1: rx_len_cntr-rx_len_cntr_arch
	Info (12023): Found entity 1: rx_len_cntr
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/rx_get_data.vhd
	Info (12022): Found design unit 1: rx_get_data-rx_get_data_arch
	Info (12023): Found entity 1: rx_get_data
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/rx_ctrl.vhd
	Info (12022): Found design unit 1: rx_ctrl-rx_ctrl_arch
	Info (12023): Found entity 1: rx_ctrl
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/pcie_msi.vhd
	Info (12022): Found design unit 1: pcie_msi-pcie_msi_arch
	Info (12023): Found entity 1: pcie_msi
Info (12021): Found 3 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/ip_16z091_01_top.vhd
	Info (12022): Found design unit 1: ip_16z091_01_top-ip_16z091_01_top_arch
	Info (12022): Found design unit 2: ip_16z091_01_top-ip_16z091_01_top_cycv_arch
	Info (12023): Found entity 1: ip_16z091_01_top
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/ip_16z091_01.vhd
	Info (12022): Found design unit 1: ip_16z091_01-ip_16z091_01_arch
	Info (12023): Found entity 1: ip_16z091_01
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/interrupt_wb.vhd
	Info (12022): Found design unit 1: interrupt_wb-interrupt_wb_arch
	Info (12023): Found entity 1: interrupt_wb
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/interrupt_core.vhd
	Info (12022): Found design unit 1: interrupt_core-interrupt_core_arch
	Info (12023): Found entity 1: interrupt_core
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/init.vhd
	Info (12022): Found design unit 1: init-init_arch
	Info (12023): Found entity 1: init
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/error.vhd
	Info (12022): Found design unit 1: error-error_arch
	Info (12023): Found entity 1: error
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_sys_arbiter.vhd
	Info (12022): Found design unit 1: vme_sys_arbiter-vme_sys_arbiter_arch
	Info (12023): Found entity 1: vme_sys_arbiter
Info (12021): Found 2 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_pkg.vhd
	Info (12022): Found design unit 1: vme_pkg
	Info (12022): Found design unit 2: vme_pkg-body
Info (12021): Found 2 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z000-00_src/source/fpga_pkg_2.vhd
	Info (12022): Found design unit 1: fpga_pkg_2
	Info (12022): Found design unit 2: fpga_pkg_2-body
Info (12021): Found 2 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/wb_pkg.vhd
	Info (12022): Found design unit 1: wb_pkg
	Info (12022): Found design unit 2: wb_pkg-body
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/wb_bus.vhd
	Info (12022): Found design unit 1: wb_bus-wb_bus_arch
	Info (12023): Found entity 1: wb_bus
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/z091_01_wb_adr_dec.vhd
	Info (12022): Found design unit 1: z091_01_wb_adr_dec-a25_arch
	Info (12023): Found entity 1: z091_01_wb_adr_dec
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/sram.vhd
	Info (12022): Found design unit 1: sram-sram_arch
	Info (12023): Found entity 1: sram
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_wbmon.vhd
	Info (12022): Found design unit 1: z126_01_wbmon-z126_01_wbmon_arch
	Info (12023): Found entity 1: z126_01_wbmon
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_wb2pasmi.vhd
	Info (12022): Found design unit 1: z126_01_wb2pasmi-z126_01_wb2pasmi_arch
	Info (12023): Found entity 1: z126_01_wb2pasmi
Info (12021): Found 2 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_wb_pkg.vhd
	Info (12022): Found design unit 1: z126_01_wb_pkg
	Info (12022): Found design unit 2: z126_01_wb_pkg-body
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_wb_if_arbiter.vhd
	Info (12022): Found design unit 1: z126_01_wb_if_arbiter-z126_01_wb_if_arbiter_arch
	Info (12023): Found entity 1: z126_01_wb_if_arbiter
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_top.vhd
	Info (12022): Found design unit 1: z126_01_top-z126_01_top_arch
	Info (12023): Found entity 1: z126_01_top
Info (12021): Found 2 design units, including 0 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_pkg.vhd
	Info (12022): Found design unit 1: z126_01_pkg
	Info (12022): Found design unit 2: z126_01_pkg-body
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_indi_if_ctrl_regs.vhd
	Info (12022): Found design unit 1: z126_01_indi_if_ctrl_regs-z126_01_indi_if_ctrl_regs_arch
	Info (12023): Found entity 1: z126_01_indi_if_ctrl_regs
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_fifo_d1.vhd
	Info (12022): Found design unit 1: z126_01_fifo_d1-z126_01_fifo_d1_arch
	Info (12023): Found entity 1: z126_01_fifo_d1
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_clk_trans_wb2wb.vhd
	Info (12022): Found design unit 1: z126_01_clk_trans_wb2wb-z126_01_clk_trans_wb2wb_arch
	Info (12023): Found entity 1: z126_01_clk_trans_wb2wb
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_switch_fab_2.vhd
	Info (12022): Found design unit 1: z126_01_switch_fab_2-z126_01_switch_fab_2_arch
	Info (12023): Found entity 1: z126_01_switch_fab_2
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_ru_ctrl.vhd
	Info (12022): Found design unit 1: z126_01_ru_ctrl-z126_01_ru_ctrl_arch
	Info (12023): Found entity 1: z126_01_ru_ctrl
Info (12021): Found 4 design units, including 2 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_pasmi/z126_01_pasmi_m25p32.vhd
	Info (12022): Found design unit 1: z126_01_pasmi_m25p32_altasmi_parallel_pn03-RTL
	Info (12022): Found design unit 2: z126_01_pasmi_m25p32-RTL
	Info (12023): Found entity 1: z126_01_pasmi_m25p32_altasmi_parallel_pn03
	Info (12023): Found entity 2: z126_01_pasmi_m25p32
Info (12021): Found 4 design units, including 2 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z126-01_src/source/z126_01_ru/z126_01_ru_cycloneiv.vhd
	Info (12022): Found design unit 1: z126_01_ru_cycloneiv_rmtupdt_73r-RTL
	Info (12022): Found design unit 2: z126_01_ru_cycloneiv-RTL
	Info (12023): Found entity 1: z126_01_ru_cycloneiv_rmtupdt_73r
	Info (12023): Found entity 2: z126_01_ru_cycloneiv
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/wbmon.vhd
	Info (12022): Found design unit 1: wbmon-wbmon_arch
	Info (12023): Found entity 1: wbmon
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/switch_fab_4.vhd
	Info (12022): Found design unit 1: switch_fab_4-switch_fab_4_arch
	Info (12023): Found entity 1: switch_fab_4
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/switch_fab_3.vhd
	Info (12022): Found design unit 1: switch_fab_3-switch_fab_3_arch
	Info (12023): Found entity 1: switch_fab_3
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/switch_fab_2.vhd
	Info (12022): Found design unit 1: switch_fab_2-switch_fab_2_arch
	Info (12023): Found entity 1: switch_fab_2
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/switch_fab_1.vhd
	Info (12022): Found design unit 1: switch_fab_1-switch_fab_1_arch
	Info (12023): Found entity 1: switch_fab_1
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/fifo_d1.vhd
	Info (12022): Found design unit 1: fifo_d1-fifo_d1_arch
	Info (12023): Found entity 1: fifo_d1
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z100-00_src/source/clk_trans_wb2wb.vhd
	Info (12022): Found design unit 1: clk_trans_wb2wb-clk_trans_wb2wb_arch
	Info (12023): Found entity 1: clk_trans_wb2wb
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z024-01_src/source/iram_wb.vhd
	Info (12022): Found design unit 1: iram_wb-iram_wb_arch
	Info (12023): Found entity 1: iram_wb
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z024-01_src/source/iram_dp_wb.vhd
	Info (12022): Found design unit 1: iram_dp_wb-iram_dp_wb_arch
	Info (12023): Found entity 1: iram_dp_wb
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z024-01_src/source/iram_av.vhd
	Info (12022): Found design unit 1: iram_av-iram_av_arch
	Info (12023): Found entity 1: iram_av
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/wbb2vme_top.vhd
	Info (12022): Found design unit 1: wbb2vme_top-wbb2vme_top_arch
	Info (12023): Found entity 1: wbb2vme_top
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_wbs.vhd
	Info (12022): Found design unit 1: vme_wbs-vme_wbs_arch
	Info (12023): Found entity 1: vme_wbs
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_wbm.vhd
	Info (12022): Found design unit 1: vme_wbm-vme_wbm_arch
	Info (12023): Found entity 1: vme_wbm
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_slave.vhd
	Info (12022): Found design unit 1: vme_slave-vme_slave_arch
	Info (12023): Found entity 1: vme_slave
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_requester.vhd
	Info (12022): Found design unit 1: vme_requester-vme_requester_arc
	Info (12023): Found entity 1: vme_requester
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_master.vhd
	Info (12022): Found design unit 1: vme_master-vme_master_arch
	Info (12023): Found entity 1: vme_master
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_mailbox.vhd
	Info (12022): Found design unit 1: vme_mailbox-vme_mailbox_arch
	Info (12023): Found entity 1: vme_mailbox
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_locmon.vhd
	Info (12022): Found design unit 1: vme_locmon-vme_locmon_arch
	Info (12023): Found entity 1: vme_locmon
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_du.vhd
	Info (12022): Found design unit 1: vme_du-vme_du_arch
	Info (12023): Found entity 1: vme_du
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_slv.vhd
	Info (12022): Found design unit 1: vme_dma_slv-vme_dma_slv_arch
	Info (12023): Found entity 1: vme_dma_slv
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_mstr.vhd
	Info (12022): Found design unit 1: vme_dma_mstr-vme_dma_mstr_arch
	Info (12023): Found entity 1: vme_dma_mstr
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_fifo.vhd
	Info (12022): Found design unit 1: vme_dma_fifo-vme_dma_fifo_arch
	Info (12023): Found entity 1: vme_dma_fifo
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_du.vhd
	Info (12022): Found design unit 1: vme_dma_du-vme_dma_du_arch
	Info (12023): Found entity 1: vme_dma_du
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_au.vhd
	Info (12022): Found design unit 1: vme_dma_au-vme_dma_au_arch
	Info (12023): Found entity 1: vme_dma_au
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma_arbiter.vhd
	Info (12022): Found design unit 1: vme_dma_arbiter-vme_dma_arbiter_arch
	Info (12023): Found entity 1: vme_dma_arbiter
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_dma.vhd
	Info (12022): Found design unit 1: vme_dma-vme_dma_arch
	Info (12023): Found entity 1: vme_dma
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_ctrl.vhd
	Info (12022): Found design unit 1: vme_ctrl-vme_ctrl_arch
	Info (12023): Found entity 1: vme_ctrl
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_bustimer.vhd
	Info (12022): Found design unit 1: vme_bustimer-bustimer_arc
	Info (12023): Found entity 1: vme_bustimer
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_au.vhd
	Info (12022): Found design unit 1: vme_au-vme_au_arch
	Info (12023): Found entity 1: vme_au
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z002-01_src/source/vme_arbiter.vhd
	Info (12022): Found design unit 1: vme_arbiter-vme_arbiter_arc
	Info (12023): Found entity 1: vme_arbiter
Info (12021): Found 6 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/a25_top.vhd
	Info (12022): Found design unit 1: A25_top-A25_top_arch
	Info (12022): Found design unit 2: z091_01_wb_master_cfg
	Info (12022): Found design unit 3: ip_16z091_01_cfg
	Info (12022): Found design unit 4: ip_16z091_01_top_cfg
	Info (12022): Found design unit 5: top_cfg
	Info (12023): Found entity 1: A25_top
Info (12021): Found 6 design units, including 3 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/16z091-01_src/source/alt_reconf/alt_reconf.vhd
	Info (12022): Found design unit 1: alt_reconf_alt_dprio_v5k-RTL
	Info (12022): Found design unit 2: alt_reconf_alt_c3gxb_reconfig_1801-RTL
	Info (12022): Found design unit 3: alt_reconf-RTL
	Info (12023): Found entity 1: alt_reconf_alt_dprio_v5k
	Info (12023): Found entity 2: alt_reconf_alt_c3gxb_reconfig_1801
	Info (12023): Found entity 3: alt_reconf
Info (12021): Found 2 design units, including 1 entities, in source file /files/projects/work/adstp/doc/vmebus/test/fpga/pcie2vme/source/pll_pcie/pll_pcie.vhd
	Info (12022): Found design unit 1: pll_pcie-SYN
	Info (12023): Found entity 1: pll_pcie
Error (10481): VHDL Use Clause error at ip_16z091_01_top.vhd(865): design library "work" does not contain primary unit "Hard_IP_x4". Verify that the primary unit exists in the library and has been successfully compiled.
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
	Error: Peak virtual memory: 5058 megabytes
	Error: Processing ended: Thu Nov 05 11:50:00 2020
	Error: Elapsed time: 00:00:11
	Error: Total CPU time (on all processors): 00:00:32
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings

 

Но qip  в \PCIe2VME\Synthesis нет.

Если все оставить как есть, то компиляция глохнет на:

Spoiler

Info: Running Quartus Prime Shell
	Info: Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition
	Info: Processing started: Thu Nov 05 11:13:07 2020
Info: Command: quartus_sh -t gen_ip_cores.tcl compile A25_top A25_top
Info: Quartus(args): compile A25_top A25_top
Info: Using INI file D:/FILES/Projects/WORK/ADSTP/DOC/VMEbus/Test/FPGA/PCIe2VME/Synthesis/quartus.ini
Info: Executing A25 pre-flow script
Info: Testing for megawizard regeneration in ../16z091-01_src/Source/x4:Hard_IP_x4
Info: Regenerating Hard_IP_x4 using qmegawiz
Info: Error:No launch command line found for megafunction wizard plug-in IP Compiler for PCI Express v16.0
Error: Executing qmegawiz: child process exited abnormally
Error (293007): Current module quartus_sh ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Altera website (http://dl.altera.com/requirements/).

 

 

 

 

 

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21 minutes ago, uzzzer said:

Info: Regenerating Hard_IP_x4 using qmegawiz Info:
Error:No launch command line found for megafunction wizard plug-in IP Compiler for PCI Express v16.0

ну вот наглядно видно, что корка pcie не генерится. Надо теперь с этим разбираться, почему

я бы вставил такие отладочные сообщения, чтобы понять, на чем именно сыпится генератор

image.thumb.png.ff4e7f05a97312ab42fa722828c3c3fe.png

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6 minutes ago, new123 said:

ну вот наглядно видно, что корка pcie не генерится. Надо теперь с этим разбираться, почему

Ну это я уже догадался:))) 

Вот, что за PCIe2VME\16z091-01_src\Source\x4\Hard_IP_x4.vhd и почему, там может все быть закоментино?

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2 minutes ago, new123 said:

добавил в сообщение метод поиска причины

Попробовал вот что вышло:

Spoiler

Info: *******************************************************************
Info: Running Quartus Prime Shell
	Info: Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition
	Info: Processing started: Thu Nov 05 12:24:34 2020
Info: Command: quartus_sh -t gen_ip_cores.tcl compile A25_top A25_top
Info: Quartus(args): compile A25_top A25_top
Info: Using INI file D:/FILES/Projects/WORK/ADSTP/DOC/VMEbus/Test/FPGA/PCIe2VME/Synthesis/quartus.ini
Info: Executing A25 pre-flow script
Info: Testing for megawizard regeneration in ../16z091-01_src/Source/x4: Hard_IP_x4 
Info: Regenerating Hard_IP_x4 using qmegawiz
Info: after delete
Info: after copy
Info: after set
Info: Error:No launch command line found for megafunction wizard plug-in IP Compiler for PCI Express v16.0
Error: Executing qmegawiz: child process exited abnormally
Error (293007): Current module quartus_sh ended unexpectedly. Verify that you have sufficient memory available to compile your design. You can view disk space and physical RAM requirements on the System and Software Requirements page of the Altera website (http://dl.altera.com/requirements/).

 

 

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Вспоминая, что у альтеры есть конкретный баг, начиная с какой то версии, в наименовании корок, возможно надо подправить название. Они начиная с какого то времени, во всех корках начали переименовывать слово Altera на Intel. 
В вашем настроечном файле, название IP Compiler for PCI Express v16.0.

Проверьте на всякий случай настоящее название. Для этого зайдите в /intelFPGA/16.0/ip/altera, там надо найти, где этот IP Compiler лежит, найти в этой папке файл .lst, открыть и посмотреть настоящее название корки, вдруг оно уже другое.

6 minutes ago, uzzzer said:

Попробовал вот что вышло:

ну вы вставьте побольше отладочных, я как пример только привел

 

update

Я посмотрел у себя. Файлик называется ip_compiler_for_pci_express_wizard.lst
У меня в 18 версии, прописаны только 18, 14 версии (у вас 16 в генераторе). Если у вас так же, наверняка в этом проблема
 

[Interface Protocols|PCI Express]
IP Compiler for PCI Express v18.0 = "%t" "%w/../../common/lib/megawizard.pl" --wizard_file:"%w/ip_toolbench/ip_compiler_for_pci_express.jar" --wizard:altera_avalon_pcie_compiler --familyParameter:deviceFamily %f %o %h
<INFO>
<ACCEPT_OTHER_CNX VALUE="ON"/>
<QIP_FILE_ENABLED/>
<DEVICE_FAMILY   SUPPORTED="NONE | Stratix IV | Stratix III | Arria II GX | Arria II GZ | Cyclone IV E | Cyclone IV GX | Cyclone III LS | Cyclone III"   SUPPORT_CHECK="ON" />
<LANGUAGES   AHDL="OFF" />
<PINPLAN SUPPORTED="OFF"/>
<ALIAS>IP Compiler for PCI Express v14.0</ALIAS>
<ALIAS>IP Compiler for PCI Express v14.1</ALIAS>
</INFO>

 

Edited by new123

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6 minutes ago, new123 said:

Вспоминая, что у альтеры есть конкретный баг, начиная с какой то версии, в наименовании корок, возможно надо подправить название. Они начиная с какого то времени, во всех корках начали переименовывать слово Altera на Intel. 
В вашем настроечном файле, название IP Compiler for PCI Express v16.0.

Проверьте на всякий случай настоящее название. Для этого зайдите в /intelFPGA/16.0/ip/altera, там надо найти, где этот IP Compiler лежит, найти в этой папке файл .lst, открыть и посмотреть настоящее название корки, вдруг оно уже другое.

ну вы вставьте побольше отладочных, я как пример только привел

 

У меня Quartus 15.1, не могу найти каталог /intelFPGA/16.0/ip/altera

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6 minutes ago, uzzzer said:

У меня Quartus 15.1, не могу найти каталог /intelFPGA/16.0/ip/altera

ну вот и причина. В настроечном файле корки у вас 16 версия прописана. Тот кто это tcl писал, у него была 16 версия наверное.
Тогда удостоверьтесь, что /intelFPGA/15.1/ip/altera/ip_compiler_for_pci_express/lib/ip_compiler_for_pci_express_wizard.lst не прописана версия 15.1 и либо добавьте ее туда в ALIAS, либо пробуйте в Hard_IP_x4.txt менять в заголовке номер версии на свою
 

-- megafunction wizard: %IP Compiler for PCI Express v16.0%

на

-- megafunction wizard: %IP Compiler for PCI Express v15.1%

 

Здесь наверное тоже надо менять. Тут уже методом тыка =)

-- Retrieval info: <MEGACORE title="IP Compiler for PCI Express"  version="16.0"  build="211"  iptb_version="1.3.0 Build 211"  format_version="120" >

 

Edited by new123

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Ну Слава Богу ! Все заработало:)

 

После вашего совета:

1 hour ago, new123 said:

 


-- megafunction wizard: %IP Compiler for PCI Express v16.0%

на


-- megafunction wizard: %IP Compiler for PCI Express v15.1%

 

Прошла полная компиляция. Сгенерились две корки:

 \PCIe2VME\16z091-01_src\Source\x1\Hard_IP_x1.qip и \PCIe2VME\16z091-01_src\Source\x4\Hard_IP_x4.qip

и бинарники PCIe2VME\Synthesis\fpga_files\16A025-00_03_15.bin с PCIe2VME\Synthesis\fpga_files\16A025-00_03_15.hex

Спасибо вам большее !

 

Вот к стати страница с этим проектом:

https://ohwr.org/project/pcie-vme-bridge/wikis/home

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