Xilinx Spartan 6 ODDR2 моделирование вывода DDR данных.

cpl 0

9 апреля, 2020

Опубликовано 9 апреля, 2020 · Жалоба

Моделирую вывод DDR данных.(Spartan 6, QuestaSim)

Наткнулся на странное поведение компонента ODDR2.

При старте моделирования ПЕРВЫЕ данные на выходе ODDR2 появляются только через 12 тактов, до этого 00.

Не пойму в чем причина, что не так делаю ?

тестбенч прилагаю.

`timescale 1ns / 1ps
module top(
    input wire         i_clk_tx_0,
    input wire         i_clk_tx_180,
    input wire         i_rst,
    output wire [5:0]  o_tx_data_ddr

    ,
    output wire [5:0] o_debug1
    ,
    output wire [5:0] o_debug2
);

reg         tx_ce = 1; // CE для ODDR2

reg [23:0] fifo_rd_data = 24'b1111_11__00_0001__1010_10__00_0010;
wire [5:0] d0;
wire [5:0] d1;

reg       rst = 0;


assign d0 = fifo_rd_data[23:18];
assign d1 = fifo_rd_data[11:6];

reg [4:0] st = 0;
reg [1:0] empty_cnt = 0;

reg [7:0] delay = 0;

always @(posedge i_clk_tx_0)
begin
    case(st)
    0:
    begin
        delay <= delay + 1'b1;
        if (delay == 2) begin
            delay <= 0;
//            rst <= 0;
            st <= st + 1'b1;
        end else begin
//            rst <= 1;
        end
    end

    1:
    begin
        delay <= delay + 1'b1;
        st <= st + 1'b1;
    end

    2:
    begin
        $display("fifo_rd_dataR = 0x%x 0x%x 0x%x 0x%x", fifo_rd_data[23:18], fifo_rd_data[17:12], fifo_rd_data[11:6], fifo_rd_data[5:0]);

        fifo_rd_data[23:12] <= fifo_rd_data[23:12] + 1'b1;
        fifo_rd_data[11:0]  <= fifo_rd_data[11:0] + 1'b1;

        if (delay == 100) st <= 3; else st <= 1;
    end

    3:
    begin
    end	 
	 
    default:
        st <= 0;
	 
endcase
end





ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst0 (
    .Q     ( o_tx_data_ddr[0] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[0]),        // 1-bit data input (associated with C0)
    .D1    ( d1[0]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);

ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst1 (
    .Q     ( o_tx_data_ddr[1] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[1]),        // 1-bit data input (associated with C0)
    .D1    ( d1[1]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);

ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst2 (
    .Q     ( o_tx_data_ddr[2] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[2]),        // 1-bit data input (associated with C0)
    .D1    ( d1[2]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);

ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst3 (
    .Q     ( o_tx_data_ddr[3] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[3]),        // 1-bit data input (associated with C0)
    .D1    ( d1[3]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);

ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst4 (
    .Q     ( o_tx_data_ddr[4] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[4]),        // 1-bit data input (associated with C0)
    .D1    ( d1[4]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);

ODDR2 #(
    .DDR_ALIGNMENT("C1"), // Sets output alignment to "NONE", "C0" or "C1"
    .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
    .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst5 (
    .Q     ( o_tx_data_ddr[5] ),     // 1-bit DDR output data
    .C0    ( i_clk_tx_180 ),  // 1-bit clock input
    .C1    ( i_clk_tx_0 ), // 1-bit clock input
    .CE    ( 1'b1),        // 1-bit clock enable input
//    .CE    ( tx_ce),       // 1-bit clock enable input
    .D0    ( d0[5]),        // 1-bit data input (associated with C0)
    .D1    ( d1[5]),        // 1-bit data input (associated with C1)
    .R     ( rst),         // 1-bit reset input
    .S     ( 1'b0)          // 1-bit set input
);



assign o_debug1 = d0;
assign o_debug2 = d1;

endmodule