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Verilog как приравнять все биты регистра к 1

Здравствуйте.

Как в verilog приравнять все биты регистра переменной длины к 1 ?

Есть вариант без for?

В vhdl так : a <= (others => '1');

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18 минут назад, Kostochkin сказал:

Здравствуйте.Как в verilog приравнять все биты регистра переменной длины к 1 ?

{Width{1'b1}} // This is equivalent to 11111 ... 1  "Width" times

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6 minutes ago, iosifk said:

{Width{1'b1}} // This is equivalent to 11111 ... 1  "Width" times

Благодарю.

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~0

-1

'1 (SystemVerilog)

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