toshas 0 Posted October 28, 2016 · Report post Неприметный, но важный AR. https://www.xilinx.com/support/answers/68006.html Some designs created in the 2016.1 and 2016.2 versions of Xilinx Design Tools have been found to have incorrect bitstreams. The root cause has been identified as a multi-threading (default) issue in write_bitstream, which can cause some configuration memory cells to be set to 0 instead of 1. CRC will still pass for these bitstreams, as the bitstream CRC is calculated using the incorrectly set values and will result in a valid check when the bitstream is loaded. All devices (7 Series, Zynq-7000, UltraScale, UltraScale+, and Zynq UltraScale+) and all OS's (Windows and Linux) are impacted by this issue. Xilinx Design Tools including Vivado, SDAccel, and SDSoC (2016.1 and 2016.2 versions) are impacted. Multi-threading is turned off for write_bitstream in Vivado 2016.3, SDAccel 2016.3 and SDSoC 2016.3, so this issue will not occur for those versions and later. Quote Ответить с цитированием Share this post Link to post Share on other sites
Flood 0 Posted October 28, 2016 · Report post Мда. Серьезный баг. Спасибо! Quote Ответить с цитированием Share this post Link to post Share on other sites
Dimidrol 0 Posted October 28, 2016 · Report post Проверил свой проект, ошибок не обнаружилось. Quote Ответить с цитированием Share this post Link to post Share on other sites
