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Quartus 10.0-13.0 : Verilog HDL Loop error

set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT ххх

 

не работает ни через .qsf ни через "Assignment -> Settings -> Analysis&Synthesis -> More Settings ... -> Iteration limit for constant Verilog loops"

 

у меня у одного такие проблемы или нет?

 

На 9.1sp2 - задается и работает, проблема в том, что новый проект с чипом C4GX, а его 9ка не поддерживает

 

Требуется подсчитать значение параметра(значение ПСП-28 с большим сдвигом), квартус стопорится с ошибкой:

"Error (10106): Verilog HDL Loop error at mpsp.v(6): loop must terminate within 5000 iterations"

 

function int mpsp(input int value, input int psp_type, input int times);
   bit [31:0] rpsp;
begin
   rpsp = value;

   for (int i = 0; i < times; i = i + 1)//Error : Verilog HDL Loop error
   begin
       case (psp_type)
        2: rpsp = {rpsp[30:0], rpsp[ 1]^rpsp[ 0]};
        3: rpsp = {rpsp[30:0], rpsp[ 2]^rpsp[ 0]};
        4: rpsp = {rpsp[30:0], rpsp[ 3]^rpsp[ 0]};
        5: rpsp = {rpsp[30:0], rpsp[ 4]^rpsp[ 1]};
        6: rpsp = {rpsp[30:0], rpsp[ 5]^rpsp[ 0]};
        7: rpsp = {rpsp[30:0], rpsp[ 6]^rpsp[ 2]};
        8: rpsp = {rpsp[30:0], rpsp[ 7]^rpsp[ 3]^rpsp[2]^rpsp[1]};
        9: rpsp = {rpsp[30:0], rpsp[ 8]^rpsp[ 3]};
       10: rpsp = {rpsp[30:0], rpsp[ 9]^rpsp[ 2]};
       11: rpsp = {rpsp[30:0], rpsp[10]^rpsp[ 1]};
       12: rpsp = {rpsp[30:0], rpsp[11]^rpsp[ 5]^rpsp[3]^rpsp[0]};
       13: rpsp = {rpsp[30:0], rpsp[12]^rpsp[ 3]^rpsp[2]^rpsp[0]};
       14: rpsp = {rpsp[30:0], rpsp[13]^rpsp[ 9]^rpsp[5]^rpsp[0]};
       15: rpsp = {rpsp[30:0], rpsp[14]^rpsp[ 0]};
       16: rpsp = {rpsp[30:0], rpsp[15]^rpsp[11]^rpsp[2]^rpsp[0]};
       17: rpsp = {rpsp[30:0], rpsp[16]^rpsp[ 2]};
       18: rpsp = {rpsp[30:0], rpsp[17]^rpsp[ 6]};
       19: rpsp = {rpsp[30:0], rpsp[18]^rpsp[ 4]^rpsp[1]^rpsp[0]};
       20: rpsp = {rpsp[30:0], rpsp[19]^rpsp[ 2]};
       21: rpsp = {rpsp[30:0], rpsp[20]^rpsp[ 1]};
       22: rpsp = {rpsp[30:0], rpsp[21]^rpsp[ 0]};
       23: rpsp = {rpsp[30:0], rpsp[22]^rpsp[ 4]};
       24: rpsp = {rpsp[30:0], rpsp[23]^rpsp[ 6]^rpsp[1]^rpsp[0]};
       25: rpsp = {rpsp[30:0], rpsp[24]^rpsp[ 2]};
       26: rpsp = {rpsp[30:0], rpsp[25]^rpsp[ 5]^rpsp[1]^rpsp[0]};
       27: rpsp = {rpsp[30:0], rpsp[26]^rpsp[ 4]^rpsp[1]^rpsp[0]};
       28: rpsp = {rpsp[30:0], rpsp[27]^rpsp[ 2]};
       default : rpsp = 0;
       endcase
   end

   mpsp = rpsp;
end
endfunction

Edited by Dimentius

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Ответ "Альтеры" (спасибо Роману Золотухо):

 

In Quartus 9x, there was no limitation on the loop constant setting.

However, this depth is being translated into a length and is part of

a decision in the tool to determine if an infinite loop exists.

Our magic number for loop iterations is not to exceeds the 5000 iteration,

else it is interpretted as an infinite loop.

 

Regret to inform you that, this issue had been reported to the software

team and they do not plan to change the operation.

 

 

---

 

значение VERILOG_CONSTANT_LOOP_LIMIT в "Ква QT" можно только уменьшить, максимальное значение 5000

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