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В 12.1 при разводке DDR2 вылезли следующие варнинги, которых не было в 11.0:


Critical Warning: Warning (307056): Register qsys1:qsys_inst|qsys1_ddr2_bot:ddr2_bot|qsys1_ddr2_bot_controller_phy:qsys1_ddr2_bot_controller_phy_inst|qsys1_ddr2_bot_phy:qsys1_ddr2_bot_phy_inst|qsys1_ddr2_bot_phy_alt_mem_phy:qsys1_ddr2_bot_phy_alt_mem_phy_inst|qsys1_ddr2_bot_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_h9h:auto_generated|input_cell_h[0] fed by pin ddr2t_clk_p must be placed in adjacent LAB X:33 Y:1 instead of X:33 Y:2

Critical Warning: Warning (307037): Pin ddr2t_clk_p does not use expected routing to qsys1:qsys_inst|qsys1_ddr2_bot:ddr2_bot|qsys1_ddr2_bot_controller_phy:qsys1_ddr2_bot_controller_phy_inst|qsys1_ddr2_bot_phy:qsys1_ddr2_bot_phy_inst|qsys1_ddr2_bot_phy_alt_mem_phy:qsys1_ddr2_bot_phy_alt_mem_phy_inst|qsys1_ddr2_bot_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_h9h:auto_generated|input_cell_h[0]



Не могу понять чего он от них хочет? Словно он хочет превратить их в lvds.





Еще появились неведомые:


Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions

Critical Warning: See violated timing model assumptions in previous timing analysis above



С ними че делать?


















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