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amir

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  1. Hi all I am searching for I-E-C 61000 series standards. does any body know where can I find and download them? regards
  2. JTAGICE mkII

    ли кто-либо иметь схему Atmel JTAGICE mkII?
  3. try this: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; entity divide is port ( clk : in std_logic; sign : in std_logic; divider : in std_logic_vector(31 downto 0); dividend : in std_logic_vector(31 downto 0); reminder : out std_logic_vector(31 downto 0); quotient : out std_logic_vector(31 downto 0); ready : out std_logic ); end divide; architecture div of divide is constant Z32 : std_logic_vector(31 downto 0) := (others => '0'); constant Z31 : std_logic_vector(30 downto 0) := (others => '0'); signal QuotientReg, QuotientTemp : std_logic_vector(31 downto 0); signal Difference, DividendCopy, DividerCopy : std_logic_vector(63 downto 0); signal ready_internal : std_logic; signal BitReg : integer range 0 to 63 := 0; signal NegativeOutput : std_logic := '0'; function shl(ARG: std_logic_vector) return std_logic_vector is variable ARG_length: INTEGER := ARG'length-1; variable result : std_logic_vector(ARG_length downto 0); begin result := ARG(ARG_length-1 downto 0) & '0'; return result; end function; function shr(ARG: std_logic_vector) return std_logic_vector is variable ARG_length: INTEGER := ARG'length-1; variable result: std_logic_vector(ARG_length downto 0); begin result := '0' & ARG(ARG_length downto 1); return result; end function; function wnor(ARG: std_logic_vector) return std_logic is variable input_len: INTEGER := ARG'length; variable result,temp : std_logic := '0'; begin for i in 0 to input_len-1 loop temp := temp or arg(i) ; end loop; result := not temp; return result; end function; begin ready <= ready_internal; quotient <= QuotientReg; ready_internal <= wnor(conv_std_logic_vector(BitReg,6)); Reminder <= DividendCopy(31 downto 0) when (NegativeOutput = '0') else ((not DividendCopy(31 downto 0)) + '1'); process (clk,ready_internal,sign,BitReg) begin if (clk='1' and clk'event) then if (ready_internal = '1') then BitReg <= 32; QuotientReg <= (others => '0'); QuotientTemp <= (others => '0'); if ( (sign = '0') or (dividend(31) = '0') ) then DividendCopy <= Z32 & Dividend; else DividendCopy <= Z32 & ((not Dividend) + '1'); end if; if ( (sign = '0') or (divider(31) = '0') ) then DividerCopy <= '0' & Divider & Z31; else DividerCopy <= '0' & ((not Divider) + '1') & Z31; end if; NegativeOutput <= sign and ((divider(31) and not(dividend(31))) or (not(divider(31)) and dividend(31)) ); elsif (BitReg > 0) then Difference <= DividendCopy - DividerCopy ; QuotientTemp <= shl (QuotientTemp); if (Difference(63) = '0') then DividendCopy <= Difference; QuotientTemp(0) <= '1' ; end if; if (NegativeOutput='0') then QuotientReg <= QuotientTemp ; else QuotientReg <= (not QuotientTemp) + '1' ; end if; DividerCopy <= shr (DividerCopy); BitReg <= BitReg - 1 ; end if; end if; end process; end div;
  4. why don't you use xhdl? ENTITY divide IS PORT ( ready : OUT std_logic; quotient : OUT std_logic_vector(31 DOWNTO 0); remainder : OUT std_logic_vector(31 DOWNTO 0); dividend : IN std_logic_vector(31 DOWNTO 0); divider : IN std_logic_vector(31 DOWNTO 0); sign : IN std_logic; clk : IN std_logic); END divide; ARCHITECTURE arch OF divide IS SIGNAL quotient_temp : std_logic_vector(31 DOWNTO 0); SIGNAL dividend_copy : std_logic_vector(63 DOWNTO 0); SIGNAL divider_copy : std_logic_vector(63 DOWNTO 0); SIGNAL diff : std_logic_vector(63 DOWNTO 0); SIGNAL negative_output : std_logic; SIGNAL temp_xhdl4 : std_logic_vector(31 DOWNTO 0); SIGNAL remainder_xhdl2 : std_logic_vector(31 DOWNTO 0); SIGNAL bit : std_logic_vector(5 DOWNTO 0); SIGNAL ready_xhdl3 : std_logic; SIGNAL temp_xhdl5 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl6 : std_logic_vector(63 DOWNTO 0); SIGNAL temp_xhdl7 : std_logic_vector(31 DOWNTO 0); SIGNAL quotient_xhdl1 : std_logic_vector(31 DOWNTO 0); BEGIN quotient <= quotient_xhdl1; remainder <= remainder_xhdl2; ready <= ready_xhdl3; temp_xhdl4 <= dividend_copy(31 DOWNTO 0) WHEN (NOT negative_output) = '1' ELSE NOT dividend_copy(31 DOWNTO 0) + "00000000000000000000000000000001"; remainder_xhdl2 <= temp_xhdl4 ; ready_xhdl3 <= NOT bit ; PROCESS VARIABLE xhdl_initial : BOOLEAN := TRUE; BEGIN IF (xhdl_initial) THEN bit <= "000000"; xhdl_initial := FALSE; ELSE WAIT; END IF; END PROCESS; PROCESS VARIABLE xhdl_initial : BOOLEAN := TRUE; BEGIN IF (xhdl_initial) THEN negative_output <= '0'; xhdl_initial := FALSE; ELSE WAIT; END IF; END PROCESS; temp_xhdl5 <= "00000000000000000000000000000000" & dividend WHEN (NOT sign OR NOT dividend(31)) = '1' ELSE "00000000000000000000000000000000" & NOT dividend + "00000000000000000000000000000001"; temp_xhdl6 <= '0' & divider & "0000000000000000000000000000000" WHEN (NOT sign OR NOT divider(31)) = '1' ELSE '0' & NOT divider + "00000000000000000000000000000001" & "0000000000000000000000000000000"; temp_xhdl7 <= quotient_temp WHEN (NOT negative_output) = '1' ELSE NOT quotient_temp + "00000000000000000000000000000001"; PROCESS BEGIN WAIT UNTIL (clk'EVENT AND clk = '1'); IF (ready_xhdl3 = '1') THEN bit <= "100000"; quotient_xhdl1 <= "00000000000000000000000000000000"; quotient_temp <= "00000000000000000000000000000000"; dividend_copy <= temp_xhdl5; divider_copy <= temp_xhdl6; negative_output <= sign AND ((divider(31) AND NOT dividend(31)) OR (NOT divider(31) AND dividend(31))); ELSE IF (bit > "000000") THEN diff <= dividend_copy - divider_copy; quotient_temp <= ShiftLeft(quotient_temp, 1); IF (NOT diff(63) = '1') THEN dividend_copy <= diff; quotient_temp(0) <= '1'; END IF; quotient_xhdl1 <= temp_xhdl7; divider_copy <= ShiftRight(divider_copy, 1); bit <= bit - "000001"; END IF; END IF; END PROCESS; END arch;
  5. I had a board which has two sot-143 parts on. Because of a mistake, these two components were removed and their pins broken. Now I want to replace them. But I do not Know actually what are they. Their designators on pcb are "H". Does anyone know what are they? Its top view appearance is like following:
  6. Китайское хранилище

    Цитата(psygash @ Dec 7 2005, 23:12) http://file.21ic.com.cn/ ftp://ic21:21ic@file.21ic.com.cn/
  7. Цитата(serges @ Oct 30 2006, 11:47) Может кто-то знает пароль-явки на ftp.file.21ic.com.cn, заранее спасибо. ftp://ic21:21ic@file.21ic.com.cn/