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About gxlly

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  1. how to know C and O,in 6.2 there are some new moudle or components,use LND keygen to make C and O,then to generate the secfeko.dat,but the new feature is off.
  2. what about mean in O: and C: in secfeko.dat,I can make secfeko.datfor 6.x,but it is not full.
  3. I have version 3.7,where is 3.8?
  4. you can download from: / -=TLF=- / aux / up /using/ by mtang/com3. / in using /prn6 / .lpt /for TLF/CST.Studio.Suite.v2008.SP3.DVD-SHooTERS/
  5. Problems Fixed in PADS2007 Update 2 PADS2007 Update 2 contains all fixes included in Update1, and one additional fix for PADS Layout. New Fix in Update 2 PADS Layout .. DR 399563 - Pin Sequence is reset to default 1-??, after exporting ASCII starting with v2005.2 Description: Conversion of PADS2007 Layout Designs to older versions such as PADS2005 SPac3 and earlier through the ASCII file interface can cause the unintentional swapping of data on pins including: Pin types Pin names Swap types Signal Pin nets Important: ASCII out of and into PADS Layout using the current PADS2007 ASCII format does not introduce changes to pin data. The following issues are applicable ONLY if you have converted your design via ASCII to a version of PADS prior to PADS2007. Issues Most designs will not display errors. The following information is provided to indicate the effects of the issue and also to indicate functionality which is not affected: Pin Types are used primarily when analyzing PADS Layout designs in the HyperLynx Boardsim product. Pin Types are used by Layout only under Routing Length Minimization types Serial Source, Parallel Source and Middriven for high speed nets, and display only if a pin property is viewed. Pin type errors do not affect design connectivity in PADS Layout. Pin type information is stored in the library component. PADS2007 Update 2 Release Notes 3 June 2007 Pin Names are used primarily in PADS Logic and have no effects in PADS Layout. Pin name data is stored in the library component. Swap types are used by ECO routines to allow or inhibit swapping of pins within a component. Users may be able to manually initiate incorrect pin swaps in ECO mode between pins which are defined as not swappable in the library if a component has the error. Pin name data is stored in the library component. Signal pin nets are used by PADS Layout only during the reading of a netlist from a schematic capture package such as PADS Logic or DxDesigner to connect pins having the same nets. ASCII out of a PADS Layout design to an older version and reading the design back into Layout does not automatically connect signal pin. Existing net connectivity is not affected by this error. Signal pin data is stored in the library component. Comparison of a Layout design to an ASCII file, a different Layout design, or a schematic using ECO routines is not affected by these errors. An erroneous part manually saved to a library from a PCB design in PADS Layout could overwrite an existing part definition. This could lead to connectivity issues if the part is used to create a schematic. Summary In most cases users will not experience these errors. This update is being provided to avoid overwriting correct pin data in library parts if a component is merged from a PADS Layout design to a user's library. Tech Note and Repair Script Download For more detailed information, including a location from which you can download a script that will check for and correct these errors, see Tech Note mg79023 – PADS Layout pin errors when ASCII out to previous releases 4 PADS2007 Update 2 Release Notes June 2007 Fixed in Update 1 PADS Layout .. DR 392157 - Connectivity check may show non-existent errors on stitching vias. Description: In some designs with stitching vias non-existant errors are displayed when running Connectivity checking. Connectivity checking is not ommiting the display of real connectivity errors but it may display false errors when none exist. .. DR 393506 - Step and repeat in decal editor does not accept the "." character which is critical for use of millimeters. Description: In Decal Editor, adding a pad and using the Repeat RMB command, the Distance field does not accept "." character to allow metric use. When typing a metric value you will receive an error message. .. DR 392733 - Move verb mode not remaining active when using the SS command to select components to move. Description: The Move verb mode no longer stays active after the SS (Search and Select) modeless command is used to find and select a component. .. DR 391380 - Reports Netlist w/o pin information, Netlist w/pin information, PowerPCB V3.0 Format Netlist or PowerPCB V2.0 increment pin numbers by one. Description: The output for these reports are incrementing pin numbers for each component by one. Netlist output and ASCII ouput are not affected. .. DR 390744 - Padstacks require a "." character before or after a decimal number in metric. Description: When editing Padstacks in PADS2005 entries such as .33 or .21 are allowed but PADS2007 requires entries such as 0.33 and 0.21 PADS2007 Update 2 Release Notes 5 June 2007 .. DR 399093 - CAM Drill Drawing setup nulls drill count for NP drills, and re-sets NP to plated Description: The Drill table listing in CAM may not display and sort the contents correctly after an existing symbol has been changed to a new symbol. .. DR 395845 - Program crashes for any nets with 40 or more characters added to the View List in Assign > Nets Description: In some instances modification or viewing of nets with 40 or more characters in the View > Nets dialog may cause Layout to fail. .. DR 395016 - Forward Annotation from Dx to PADS is overwriting default fanout rules in the PCB database Description: Component rules comparisons between DxDesigner and PADS Layout or PADS Logic and PADS Layout may cause an existing Layout component rules value to be set to zero if the value is set in Layout and the value is not set in eith the DxDesigner or Logic schematic. .. DR 394712 - Creation of CAM350 files may cause Layout to fail. Description: In some instances use of the CAM350 Link may cause Layout to fail .. DR 397887 - Fatal error with complex copper Description: In some instances manipulation and CAM output of complex copper may cause the Layout to fail. PADS Router .. DR 393829 - In case of multiple via styles, the interactive router use the smallest via size, regardless of the selected via type. Description: Interactive routing in PADS Router is always selecting the smallest via to be placed. This error requires the user to either restrict certain via types prior to routing or they must re-select placed vias and change them to a larger size manually. PADS Logic .. DR 388691 - The default rule setting for "Maximum number of Vias" is set to zero in PADS Logic for all new schematics started in PADS2007. 6 PADS2007 Update 2 Release Notes June 2007 Description: When creating a new Logic schematic the maximum number of vias allowed in rules is set to zero which when translated to Router inhibits routing. The user must manually change the rules in the design to a value larger than zero to allow Routing in PADS Router. .. DR 399630 - Fatal run-time error, while exporting ASCII in Logic Description: In some cases a design with many rules in PADS Logic will fail during rules manipulation or ASCII out. .. DR 398734 - Printing on pdf printer (with Adobe Professional 7.0) the result is not scaled 1 to 1, but is reduced to half of the page. Description: PDF out using an Adobe printer driver and regular printing output to a laser printer may not scale to the full extents of the allowable plotting area. Logic interprets the plotting area to be smaller than the available space. The higher the resolution of the output device the greater the plotting area will be reduced. Printing using the Scale to Fit command will generate ouput smaller than the available sheet size. http://listserver.pads.com/read/attachment...0Update%202.doc hxxp://rapidshare.com/files/101461700/P-A-D-S-2007-update2_by_gxlly_for__electronix_.zip.html
  6. CADSTAR 10 Powerful design tools developed with ease of use in mind for the PCB designer and the PCB engineer. It has never been easier to control your PCB or Schematic design. The enhanced CADSTAR design modules offer features such as: Version control for Components & Symbols (both in PCB and Schematic); Intelligent busses Support of Rules by Area in Design Editor User-defined Attributes for Components & Symbols Automatic Library reload Even more windows-compliant functionalities like multiple color choice and function key definition. you can use patch from LONG.