вот оно последствие VHDL :)))
взял ваш алгоритм, делал на стратиксе 3, спидгрейт 4.
ваш показал 190 МГЦ,
чуть подправил
module mlogtabdiv2 (input rst, clk, input [19:0] in, output logic [5:0] out);
localparam int unsigned cTAB_CODE [0 : 63] = '{
1, 1,2,2,3,3,4,5,6,
8,10,13,16,20,25,32,40,
50,63,79,100,126,158,200,251,
316,398,501,631,794,1000,1259,1585,
1995,2512,3162,3981,5012,6310,7943,10000,
12589,15849,19953,25119,31623,39811,50119,63096,
79433,100000,125893,158489,199526,251189,316228,398107,
501187,630957,794328,1000000,1000000,1000000,1000000
};
logic [5 : 0] index1;
logic [5 : 0] index2;
logic [5 : 0] index3;
logic [5 : 0] index4;
logic [5 : 0] index5;
logic [19 : 0] reg1;
logic [19 : 0] reg2;
logic [19 : 0] reg3;
logic [19 : 0] reg4;
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
index1 <= 32;
index2 <= 32;
index3 <= 32;
index4 <= 32;
index5 <= 32;
reg1 <= '0;
reg2 <= '0;
reg3 <= '0;
reg4 <= '0;
out <= '0;
end
else begin
reg1 <= in;
if (in == cTAB_CODE[32])
index1 <= 32;
else if (in < cTAB_CODE[32])
index1 <= 16;
else
index1 <= 48;
//
reg2 <= reg1;
if (reg1 == cTAB_CODE[index1])
index2 <= index1;
else if (reg1 < cTAB_CODE[index1])
index2 <= index1 - 8;
else
index2 <= index1 + 8;
//
reg3 <= reg2;
if (reg2 == cTAB_CODE[index2])
index3 <= index2;
else if (reg2 < cTAB_CODE[index2])
index3 <= index2 - 4;
else
index3 <= index2 + 4;
//
reg4 <= reg3;
if (reg3 == cTAB_CODE[index3])
index4 <= index3;
else if (reg3 < cTAB_CODE[index3])
index4 <= index3 - 2;
else
index4 <= index3 + 2;
//
if (reg4 == cTAB_CODE[index4])
index5 <= index4;
else if (reg4 < cTAB_CODE[index4])
index5 <= index4 - 1'b1;
else
index5 <= index4 + 1'b1;
//
out <= index5 - 1'b1;
end
end
endmodule
получил 208 МГц
подправил чуть больше
assign index1 = in_eq ? 32 : (in_less_eq ? 16 : 48 );
assign index2 = reg1_eq ? index1_reg : (reg1_less_eq ? index1_reg - 8 : index1_reg + 8 );
assign index3 = reg2_eq ? index2_reg : (reg2_less_eq ? index2_reg - 4 : index2_reg + 4 );
assign index4 = reg3_eq ? index3_reg : (reg3_less_eq ? index3_reg - 2 : index3_reg + 2 );
assign index5 = reg4_eq ? index4_reg - 1 : (reg4_less_eq ? index4_reg - 2 : index4_reg + 0 );
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
in_eq <= 1'b0;
in_less_eq <= 1'b0;
reg1_eq <= 1'b0;
reg1_less_eq <= 1'b0;
reg2_eq <= 1'b0;
reg2_less_eq <= 1'b0;
reg3_eq <= 1'b0;
reg3_less_eq <= 1'b0;
reg4_eq <= 1'b0;
reg4_less_eq <= 1'b0;
index1_reg <= 32;
index2_reg <= 32;
index3_reg <= 32;
index4_reg <= 32;
reg1 <= '0;
reg2 <= '0;
reg3 <= '0;
reg4 <= '0;
out <= '0;
end
else begin
reg1 <= in;
in_eq <= (in == cTAB_CODE[32]);
in_less_eq <= (in < cTAB_CODE[32]);
//
reg2 <= reg1;
reg1_eq <= (reg1 == cTAB_CODE[index1]);
reg1_less_eq <= (reg1 < cTAB_CODE[index1]);
index1_reg <= index1;
//
reg3 <= reg2;
reg2_eq <= (reg2 == cTAB_CODE[index2]);
reg2_less_eq <= (reg2 < cTAB_CODE[index2]);
index2_reg <= index2;
//
reg4 <= reg3;
reg3_eq <= (reg3 == cTAB_CODE[index3]);
reg3_less_eq <= (reg3 < cTAB_CODE[index3]);
index3_reg <= index3;
//
reg4_eq <= (reg4 == cTAB_CODE[index4]);
reg4_less_eq <= (reg4 < cTAB_CODE[index4]);
index4_reg <= index4;
//
out <= index5;
end
end
получил 248 МГц.
все это не меняя алгоритм.
