update
https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx14_1/plugin_ism.pdf стр 82
Limitations
HWCoSim has the following limitations:
• Only one instance in a design can be selected for hardware co-simulation, and it
cannot be the top-level test bench itself.
• The selected instance for hardware co-simulation must be able to be synthesized
using XST, and must be able to be implemented on the target FPGA device of the
selected board.
The lockstep hardware co-simulation has additional restrictions on clocking and I/Os:
• The co-simulation instance in hardware is clocked with an emulated clock source that
ISim controls, and is asynchronous to the simulation. Thus, the co-simulation does not
exactly model the design scenario running in hardware, or serve as a timing
simulation.
• The instance under co-simulation cannot have access to external I/Os or
Multi-Gigabit Transceivers (MGTs), nor can it instantiate primitives (such as DCMs/
PLLs) that require a continuous clock or a clock at a specific frequency.
• All ports of the instance under co-simulation must be routable to a slice register or
LUT. Certain resources on the FPGA require dedicated routes, such as to an IOB or to
certain port of a primitive, and thus cannot be wired to any port of the instance under
co-simulation.
Задам с тестбенча второй клок...
