eternal_nan

Excellent book on processor design (not architecture): Modern Processor Design: Fundamentals of Superscalar Processors John Shen, Carnegie Mellon University Mikko Lipasti, University of Wisconsin-Madison The above focuses on logical design. The best physical leaning book is: Design of High-Performance Microprocessor Circuits [Hardcover] Anantha Chandrakasan (Editor), William J. Bowhill (Editor), Frank Fox (Editor) Both excellent. The upper book is a perfect companion to the course you linked to. Ljubisa

Я бы с удовольствием но у меня нету копии, я даже не знаю как скачать такую презентацию с techonline. Регистрирожатся на techonline.com ничего не стоит (free). Извините што не могу помоч.

Не хуже но помагает не много. Ховард Джонсон сделал студию, можете почитать сдесь: http://www.commsdesign.com/design_corner/s...cleID=171202360 и seminar2.techonline.com/s/xilinx_jun0705 Единственое хорошее решение покупать корпус с много пинов для питания/земли.

все ясно по вапросу изменения параметров с напрязением, температурой, техпроцессом. Скажем што я хочу не более 10пс точности в худшем случае. Значит 4-5пс точности в лучшем. Ето в асик легко сделать, ж плис немножко труднее кажется :)

Can someone enlighten me about what "5-ya priyomka" means? I saw it in several topics already and am curious about what it means.

To clarify the question: I need to build a controllable delay line entirely on chip (no going out to the board). I guess the obvious solution is to string up a bunch of luts in a big distributed multiplexer and use the selects on the multiplexer to select the delay. The problem with that approach is that it is nowhere near the precision I need. The sort of thing that I could use to generate the more precise controllability is: 1. Use LUTs as buffers with the same signal being hooked up to all LUT inputs and select which input is taken to output - there are always small delay differences for the different path due to different circuitry, but I am not sure what these differences are. Anyone know? 2. If I could selectably control what is hooked up to a logic elements output I should be able to change its delay. For example, a logic elements output is hooked up to a nearby logic elements input, and I can also hook it up to a long (global interconect) wire in a selectable maner thus changing its capacitance. That would do, but I can't find any options in Quartus to let me play on that kind of level. Does anyone know whether that is possible to do at all? 3. vernier delay line methods. By using two delay lines with slightly different delay element delay precise delay control can be achieved. I still need to figure this out a bit more but seems to have been used by many. The issue here is that nominally all LUTs have the same delay so I have to figure out how to build the two delay lines.

Zdravstvuyte, Nuzhno sdelat delay line s ochen tochnim kontrolyem delay v Altera Cyclone 2. Chem luche tochnost tem luche budet rabotat design (~10ps tochnost bila bi ocen horosa). 5-lut elementi v etom cyclone ~250ps delay. Mozet li kto to podskazat kakoy nibud sposob sdelat delay line tochnee 250ps? - Mozno li kak to vliyat na yomkost kotoraya vidna na vihode logic element-a (i tak menyat delay cherez LE)? - Kakie raznici v zaderszhke mezdu razlichnimi vhodami i vihodom ot 5-lut? Podskazite pozhalusta yesli znayete!

A po chemu ne polzuyetes switching regulatorom? Po kraynyey mere dlya yadra? Efficiency at LM317 i vtorogo LDO s verhu ~30%, mnogo zrut za nemnosko lucshe sum...

Druzhat huze chem fuse-based FPGA no na mnogo luchse chem drugie SRAM based FPGA (Altera). Po smotri sleduyushie ssilki: http://www.xilinx.com/esp/mil_aero/collate...n_tolerance.pdf http://groups.google.com/group/comp.arch.f...530a1d09811f4a2

Sto kasayetsa verifikaciyi, ya soglasen, no ya poka vsyo i rabotal na ogromnih cipah s >100 razrabotchikov. Yesli vsye normalniye lyudi - osibok malo, no iz moego opita obicno 90% tupovatih i 10% nadyoznih lyudey. Gauss-ovskaya distribuciya vezde v prirode :) Po voprosu transistorov, para kompaniy popitalas sdelat tool kotoriy generiruyet standard cell "on the fly" stobi soversenno podhodil situaciye. Naskolko pomnyu fokus bil na size standad cell-a, (po tipa, sdelayet BUFX1.33 jesli nado). Cadabra Zenasis Esho odna bila no ne pomnyu kak nazivalas. U nih po cemu to ne ochen polucilos na rinke.

Vot ne plohaya statya pro fir filteri, tam toze govoritsya o comb filterah kotoriye yavlyayutsya chastyu cic fltera i pochemu oni horosi: http://www.techonline.com/learning/techpaper/193103481

Da, ya tolko videl i polzovalsya takimi stuckami v slucaye osibki. Iz moego opita osibkov vsegda kucha daze yesli dostatochno normalnaya verifikaciya :) To ze neploho yesli hoces zakrit bazniye sloi chipa stobi otpravit na mask making a porabotat esho nemnozhko polzuyas tolko metaliceskimi i via sloyami. Sto kasayetsya lazera ili focused ion beam, eta horoshaya ideya yesli ne ispolzovat flip chip a wire bond packaging. Mozhno poiti esho dalse i zdelat malenkiye fpga v castyah svoego asic-a, LSI Logic v odnom momente polzovalsya takim priomom, no okazalos sto u Xilinx i Altera patenti protiv etogo i oni ih zastavili perestat nemedlenno.

V principe yesli yest gate array eco cells (eto prosto kucha transistorov svyazannih kak yomkost, no mozno perevezat ispolzuya tolko metal i sdelat lyubuyu cifrovuyu funkciyu), to tolko eto nado i stavit kak spare cell. A s nimi stoit zapolnit vsyu neispolzovanuyu ploshad na chipe. Yedinstvenaya plohaya vesh s nimi eto to sto dobavlyayut leakage po sravneniyu so sluchayem gde voobshe net zapasnoy logiki. Gate-i s fiksirovanoy funkciey tolko nado stavit yesli net gate array.

1. Prostaya interpolaciya mezdu liniyami odnogo field-a (bob) 2. Prostoye sovmesheniye liniy iz dvuh field-ov (weave) 3. motion adaptive (bob+weave) 4. motion compensated using expliit motion search 5. motion compensated using phase plane correlation http://neuron2.net/library/iscas_mbiswas.pdf http://www.videotechnology.com/old9-03.html

esli ya pravilno ponyal vopros, to eto zavisit ot kakoy request sdelayet processor, i zavisit konechno ot processora. AMD/Intel processori v principe ne mogut prosit bolshe odnogo cache line-a, eto 64byte-a, sto bez problem ukladivaetsya v odin pcie paket. esli ti smozes zastavit processor poprosit cache line iz memory mapped space-a na tvoyey pcie plate, to uvidis bolshoy payload. Yesli processor prosit paru dword-ov, stolko i polucit. V chipset v principe ne kombiniruyetsa mnozestvo request-ov.

Bez problem mozno postovit ne graficeskuyu kartu v x16 slot na vseh motherboard-ah. Stobi postavit x4 platu, nado dostat 16x->4x interposer, toze nazivayut "riser card".

yesli u tebya yest kakoy nibud specificnhniy vopros ya mogu otvetit. Esli net, mogu dobavit esho dve knigi kotoriye soderzhat mnogo informaciyi kotoruyu bi ti mog hotet: PCI System Architecture Intel Pentium 4 system architecture Hyper Transport System Architecture V nih soderzhitsya informaciya o vsem sto delayet northbridge.

Vitaliy, Otvet na vas vopros po moemu: DA. Delenie mozes sdelat tak: a/b = a * (1/b). b 8 bitnoye chislo. Znacit, jevo inverse (izvini, ne znayu slovo po russki), mozno nayti v 8 taktov posledovatelnogo delenia. Mozna i na mnogo bistreye yesli ne posledovatelno. Vot tebe kusok koda katoriy delayet "inverse" v verilog: input iClk; input iReset_N; input iClear; input iEnable; input [15:0] iRefPwr; output [15:0] oQuotient; reg [31:0] Acc; reg [15:0] RefPwr; reg [15:0] PreviousInverse; wire signed [31:0] SubResult; wire FlagSubresultLTE0; always @(posedge iClk `ASYNC_RESET_DEF) begin if(!iReset_N) begin Acc <= 17'h1_0000; RefPwr <= 16'h00ff; PreviousInverse <= 16'h00ff; end else begin if(iClear) begin RefPwr <= iRefPwr; Acc <= 17'h1_0000; PreviousInverse <= oQuotient; end else begin PreviousInverse <= PreviousInverse; RefPwr <= RefPwr; if(iEnable) Acc <= FlagSubresultLTE0 ? (Acc << 1) : ((SubResult << 1) + 1'b1); end end end assign SubResult = Acc - (RefPwr << 15); assign FlagSubresultLTE0 = SubResult[31]; assign oQuotient = Acc[15:0]; nasol to ze samoye v matlab, mozet budet legce ponyat: function result = divider (dividend, divisor) acc = dividend; for i=1:16 display i; sub_result = acc - (32768 * divisor); if(sub_result >= 0) acc = (2*sub_result) + 1; else acc = acc * 2; end end result = acc;

delta impuls legko sdelat: wire Clk; // clock/takt, tot ze na katorom rabotaet filter wire ReseT_N; reg [filter_precision-1:0] stimulus; always @(posedge iClk) begin if(!Reset_N) stimulus <= 1; // eto zavisit ot podbora cifrovoy sistemi - sto takoe odin v vasey sisteme else stimulus <= 0; end assign FilterInput = stimulus;

poproboval prostiye primer, vrode podderzivayet, no poskolyku ocen malo polzovateley mozet bit mnogo bug-ov i problem.

Sushestvuyut fpga biblioteki dlya design compiler-a (.db format) or xilinx-a i alteri. S etimi vozmozno sintezirovat v fpga s designware ili daze ispolzovat module compiler. No, mapping na vernyaka vsyo ravno budet hrenoviy potomu shto i dc i mc ne ponimayit kak optimizirovat na fpga.

Na skolko ya videl, tri-state v standard cell asic prakticheski nigde ne polzuyutsya, daze yesli yest v biblioteke. Nekotorie tuli ih ponimayut, nekotorie net. Vot neskolko problem s tri-state-ami: 1. Pri start-upe sostoyanie flop-vo kotorie drive-yat tristate enable ne vozmozno znat esli u nih sinhronniy reset, znacit nuzno ispolzovat asinhrnoniy kotoriy nepopulyaren izza problem s DFT kotorie on vizivayet. 2. Voobshe, mnogo problem s DFT. V techeniye scan-a flopy kotoriye kontroliruyut tri state enable budut dyorgatsa i mogut vkljucit vise tri-stateov v to ze vremya i vyzvat Vdd->Gnd short. V principe s nimi legko osibitsya i stoit popitatsya ne ispolzovat. Ni odna bolshaya kompaniya ih ne polzuyet v standard cell flow proyektah.

http://www.eda-utilities.com/CMOS_Transist...yout_KungFu.pdf Posmotri na stranice 17, dolzhno pomoch s inverter voprosom.

Bez problem mozhno sdelat DDR2 IO na 0.18 processe. Daze v novih processah (<90nm) DDR2 IO obychno delayut iz 0.18 transistorov (vtoroy okdsid, ili second/thick gate oxide). Izvinite yesli ya ploho po Russki. DDR2 rabotaet na 1.8V, sto kak raz podhodit 0.18 transistoram. Nada budet sdelat: 1. Single ended address, command pady na 266MHz operaciu 2. Single ended data padi, na 533MHz operaciu (izza DDR rezhima) 3. Differential DQS (strobe) i clock pady 4. DLL (delay locked loop) shtobi sdvigat vhodyashie stoby (DQS linii na 1/4 clock cycle-a) V obshem, ochen mnogo raboti. V TSMC uze yest takie pady, kak i u mnogih drugih IP kompaniy. K tomu ze, trudno testirovat/otlazhivat DDR2 interface. Yesli yest denygi, pokupay gotoviy.

Izvinite, ja postavil ssilku no tolka potom videl sto ti prosis tolyka ot versii 2005 i pozhe.