Т.е. всё за вас сделать самому? Ладно.
// ODDR2 : In order to incorporate this function into the design,
// Verilog : the forllowing instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (ODDR2_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. Delete or comment
// : out inputs/outs that are not necessary.
// <-----Cut code below this line---->
// ODDR2: Output Double Data Rate Output Register with Set, Reset
// and Clock Enable.
// Spartan-6
// Xilinx HDL Language Template, version 14.7
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(generate_new_address), // 1-bit DDR output data
.C0(clk_in), // 1-bit clock input
.C1(~clk_in), // 1-bit clock input
.CE(ram_enable), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(R), // 1-bit reset input
.S(S) // 1-bit set input
);
