Перейти к содержанию

LAMT25

Новичок
  • Публикаций

    2
  • Зарегистрирован

  • Посещение

Репутация

0 Обычный
  1. Цитата(Driver_GV @ May 10 2018, 09:10) Вероятно уровень "1" входного сигнала низкий и при питании 4 вольта он определяется как 1 а при питании 5 вольт это еще ноль. Входные уровни PIC Input High Voltage I/O ports with TTL buffer 2.0V 4.5V<VDD<5.5V 0.25 VDD +0.8V 1.8V<VDD<4.5V Большое спасибо, коллега, Вы абсолютно правы.
  2. // CONFIG1 #pragma config FEXTOSC = OFF // FEXTOSC External Oscillator mode Selection bits (Oscillator not enabled) #pragma config RSTOSC = HFINT1 // Power-up default value for COSC bits (HFINTOSC (1MHz)) #pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled) #pragma config CSWEN = ON // Clock Switch Enable bit (The NOSC and NDIV bits cannot be changed by user software) #pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is enabled) // CONFIG2 #pragma config MCLRE = ON // Master Clear Enable bit (MCLR/VPP pin function is MCLR; Weak pull-up enabled) #pragma config PWRTE = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config WDTE = SWDTEN // Watchdog Timer Enable bits (WDT controlled by the SWDTEN bit in the WDTCON register) #pragma config LPBOREN = OFF // Low-power BOR enable bit (ULPBOR disabled) #pragma config BOREN = ON // Brown-out Reset Enable bits (Brown-out Reset enabled, SBOREN bit ignored) #pragma config BORV = LOW // Brown-out Reset Voltage selection bit (Brown-out voltage (Vbor) set to 2.45V) #pragma config PPS1WAY = ON // PPSLOCK bit One-Way Set Enable bit (The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle) #pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a Reset) #pragma config DEBUG = OFF // Debugger enable bit (Background debugger disabled) // CONFIG3 #pragma config WRT = OFF // User NVM self-write protection bits (Write protection off) #pragma config LVP = ON // Low Voltage Programming Enable bit (Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.) // CONFIG4 #pragma config CP = OFF // User NVM Program Memory Code Protection bit (User NVM code protection disabled) #pragma config CPD = OFF // Data NVM Memory Code Protection bit (Data NVM code protection disabled) #include <stdio.h> #include <stdlib.h> #include <pic16f18326.h> #include <xc.h> #define bOn PORTAbits.RA5 // unsigned char ucFSMstend=0; void initSystem(void) { OSCCON1 = 0b01100000; OSCFRQ = 0b00000111; // 32 MHz //OSCFRQ = 0b00000110; // 16 MHz //OSCFRQ = 0b00000100; // 8 MHz TRISAbits.TRISA0 = 0; //out8 TRISAbits.TRISA1 = 0; //out7 TRISAbits.TRISA2 = 0; //out6/ /TRISAbits.TRISA3 = 1; // TRISAbits.TRISA4 = 1; // RA4 - input OldDischarge(reserv)) TRISAbits.TRISA5 = 1; // RA5 - input OnChargFire ANSELA = 0b00000000; // all RA - digit pins TRISCbits.TRISC0 = 0; // out5 TRISCbits.TRISC1 = 0; // out4 TRISCbits.TRISC2 = 0; // out3 TRISCbits.TRISC3 = 0; // out2 TRISCbits.TRISC4 = 0; // out1 TRISCbits.TRISC5 = 0; // out redy ANSELC = 0x00; WDTCON = 0b00001110; // Watchdog interval 128 ms, watchdog OFF WDTCONbits.SWDTEN = 1; // Watchdog ON } int main(int argc, char** argv) { initSystem(); while(1){ if(bOn) LATC=0xFF; else LATC=0x00; asm("clrwdt"); }// for test