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clk

clock_source v9.1

Parameters clockFrequency 64000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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nios

altera_nios2 v9.1

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 3 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType External setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave onchip_memory_instr.s1 resetOffset 0 muldiv_multiplierType NoneSmall muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Fast icache_size _2048 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave onchip_memory_instr.s1 exceptionOffset 32 debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false cpuReset false cpuID 0 clockFrequency 64000000 breakSlave nios.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 64000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 2048 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x1020 RESET_ADDR 0x1000 BREAK_ADDR 0x2820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 0 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 14 DATA_ADDR_WIDTH 14 EIC_PRESENT NUM_OF_SHADOW_REG_SETS 3

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nios_interrupt_vector

altera_nios_custom_instr_interrupt_vector v6.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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vic

altera_vic v9.1

Parameters NUMBER_OF_INT_PORTS 16 RIL_WIDTH 4 DAISY_CHAIN_ENABLE 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DAISY_CHAIN_ENABLE 0 NUMBER_OF_INT_PORTS 16 RIL_WIDTH 4

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onchip_memory_instr

altera_avalon_onchip_memory2 v9.1

Parameters allowInSystemMemoryContentEditor false blockType M4K dataWidth 32 deviceFamily Cyclone dualPort false initMemContent true initializationFileName onchip_memory_instr instanceID NONE memorySize 4096 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "onchip_memory_instr" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "M4K" WRITABLE 1 DUAL_PORT 0 SIZE_VALUE 4096u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "M4K" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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pio_out

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 64000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 64000000u

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jtag_uart

altera_avalon_jtag_uart v9.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions NO_INTERACTIVE_WINDOWS useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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pio_tmi

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 64000000 direction Input edgeType RISING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring true simDrivenValue 0 width 16 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 1 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 16 RESET_VALUE 0x0 EDGE_TYPE "RISING" IRQ_TYPE "EDGE" FREQ 64000000u