-- VHDL Test Bench Created from source file top.vhd -- 14:44:57 05/25/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_UNSIGNED.all;



ENTITY top_bench_vhd_tb IS
END top_bench_vhd_tb;

ARCHITECTURE behavior OF top_bench_vhd_tb IS 
  
  constant PERIOD 	: time := 10 ns;
  constant HALF_PERIOD 	: time := 5000 ps;

  CONSTANT tCK       : TIME    :=  7.500 ns;
  CONSTANT addr_bits : INTEGER := 13;
  CONSTANT data_bits : INTEGER :=  8;

    COMPONENT mt46v64m8
        PORT (
            Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
            Dqs   : INOUT STD_LOGIC;
            Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
            Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
            Clk   : IN    STD_LOGIC;
            Clk_n : IN    STD_LOGIC;
            Cke   : IN    STD_LOGIC;
            Cs_n  : IN    STD_LOGIC;
            Cas_n : IN    STD_LOGIC;
            Ras_n : IN    STD_LOGIC;
            We_n  : IN    STD_LOGIC;
            Dm    : IN    STD_LOGIC
        ); 
    END COMPONENT;
  



	COMPONENT top
	PORT(
		EN_RD : IN std_logic;
		EN_WR : IN std_logic;
--		OE_RD : IN std_logic;
--		RDMODE : in std_logic;
		PWRGOOD : IN std_logic;
		SPAR3 : IN std_logic;
		set_addr : IN std_logic;
		u_clk : IN std_logic;
		u_clk_fb : IN std_logic;
		u_reset_n : IN std_logic;    
		MAIN_BUS : INOUT std_logic_vector(63 downto 0);
		ddr_dq : INOUT std_logic_vector(71 downto 0);      
		ddr_casb : OUT std_logic;
		ddr_cke : OUT std_logic;
		ddr_clk : OUT std_logic;
		ddr_clkb : OUT std_logic;
		ddr_rasb : OUT std_logic;
		ddr_web : OUT std_logic;
		CHIPSEL : OUT std_logic_vector(15 downto 0);
		ddr_ad : OUT std_logic_vector(12 downto 0);
		ddr_ba : OUT std_logic_vector(1 downto 0);
		ddr_dm : OUT std_logic_vector(8 downto 0);
		ddr_dqs : OUT std_logic_vector(8 downto 0)
		);
	END COMPONENT;

    FOR ALL : mt46v64m8 USE ENTITY work.mt46v64m8(behave);

--    SIGNAL pDq       : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
--    SIGNAL pDqs      : STD_LOGIC;
--    SIGNAL pAddr     : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
--    SIGNAL pBa       : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
--    SIGNAL pClk      : STD_LOGIC := '0';
--    SIGNAL pClk_n    : STD_LOGIC := '1';
--    SIGNAL pCke      : STD_LOGIC := '0';
--    SIGNAL pCs_n     : STD_LOGIC := '1';
--    SIGNAL pRas_n    : STD_LOGIC := '1';
--    SIGNAL pCas_n    : STD_LOGIC := '1';
--    SIGNAL pWe_n     : STD_LOGIC := '1';
    SIGNAL pDm       : STD_LOGIC := '0';



  

	SIGNAL EN_RD :  std_logic;
	SIGNAL EN_WR :  std_logic;
--	SIGNAL OE_RD :  std_logic;
	SIGNAL RDMODE :  std_logic;
	SIGNAL SPAR3 :  std_logic;
	SIGNAL RES_RD :  std_logic;
	SIGNAL POWERGOOD :  std_logic;
	SIGNAL set_addr :  std_logic;
	SIGNAL u_clk :  std_logic;
	SIGNAL u_clk_fb :  std_logic;
	SIGNAL u_reset_n :  std_logic;
	SIGNAL ddr_casb :  std_logic;
	SIGNAL ddr_cke :  std_logic;
	SIGNAL ddr_clk :  std_logic;
	SIGNAL ddr_clkb :  std_logic;
	SIGNAL ddr_rasb :  std_logic;
	SIGNAL ddr_web :  std_logic;
	SIGNAL CHIPSEL :  std_logic_vector(15 downto 0);
	SIGNAL ddr_ad :  std_logic_vector(12 downto 0);
	SIGNAL ddr_ba :  std_logic_vector(1 downto 0);
	SIGNAL ddr_dm :  std_logic_vector(8 downto 0);
	SIGNAL ddr_dqs :  std_logic_vector(8 downto 0);
	SIGNAL MAIN_BUS :  std_logic_vector(63 downto 0);
	SIGNAL ddr_dq :  std_logic_vector(71 downto 0);


signal		ddr_casbr : std_logic;
signal		ddr_cker  : std_logic;
signal		ddr_rasbr : std_logic;
signal		ddr_webr  : std_logic;
signal		ddr_adr   : std_logic_vector(12 downto 0);
signal		ddr_bar   : std_logic_vector(1 downto 0);


BEGIN
  
	uut: top PORT MAP(
		EN_RD => EN_RD,
		EN_WR => EN_WR,
--		OE_RD => OE_RD,
--		RDMODE => RDMODE,
		PWRGOOD => POWERGOOD,
		SPAR3 => SPAR3,
		set_addr => set_addr,
		u_clk => u_clk,
		u_clk_fb => u_clk_fb,
		u_reset_n => u_reset_n,
		ddr_casb => ddr_casbr,
		ddr_cke => ddr_cker,
		ddr_clk => ddr_clk,
		ddr_clkb => ddr_clkb,
		ddr_rasb => ddr_rasbr,
		ddr_web => ddr_webr,
		CHIPSEL => CHIPSEL,
		ddr_ad => ddr_adr,
		ddr_ba => ddr_bar,
		ddr_dm => ddr_dm,
		ddr_dqs => ddr_dqs,
		MAIN_BUS => MAIN_BUS,
		ddr_dq => ddr_dq
	);


    u0: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(7 downto 0),
            Dqs => ddr_dqs(0),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(0)
        );

    u1: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(15 downto 8),
            Dqs => ddr_dqs(1),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(1)
        );

    u2: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(23 downto 16),
            Dqs => ddr_dqs(2),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(2)
        );

    u3: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(31 downto 24),
            Dqs => ddr_dqs(3),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(3)
        );

    u4: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(39 downto 32),
            Dqs => ddr_dqs(4),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(4)
        );

    u5: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(47 downto 40),
            Dqs => ddr_dqs(5),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(5)
        );

    u6: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(55 downto 48),
            Dqs => ddr_dqs(6),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(6)
        );

    u7: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(63 downto 56),
            Dqs => ddr_dqs(7),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(7)
        );

    u8: mt46v64m8
        PORT MAP(
            Dq => ddr_dq(71 downto 64),
            Dqs => ddr_dqs(8),
            Addr => ddr_ad,
            Ba => ddr_ba,
            Clk => ddr_clk,
            Clk_n => ddr_clkb,
            Cke => ddr_cke,
            Cs_n => pDm,
            Ras_n => ddr_rasb,
            Cas_n => ddr_casb,
            We_n => ddr_web,
            Dm => ddr_dm(8)
        );

-- *** Test Bench - User Defined Section ***

u_clk_fb <= ddr_clk ;
                                                      
   tb : PROCESS
   BEGIN
                pDm<= '0';
		MAIN_BUS  <= (others=>'Z');
		ddr_dq  <= (others=>'Z');
		ddr_dqs  <= (others=>'Z');
 		EN_RD <='1';
		EN_WR  <='1';
--		OE_RD   <='1';
		RDMODE  <='0';
		RES_RD   <='0';
		POWERGOOD    <='1';
		SPAR3    <='1';

		set_addr  <='1';
		u_reset_n  <='0';
		
--		wait for HALF_PERIOD;
		wait for 1 ns;
		wait for (5*PERIOD);
		wait for (15*PERIOD);
		u_reset_n  <='1';
		wait for (PERIOD*250);
		wait for (PERIOD*100*4);
		wait for 1 us;
-- 		MAIN_BUS <= x"00000000006fffff";
		MAIN_BUS <= x"000000000f000000";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);


  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);

		wait for (53*PERIOD);


		MAIN_BUS <= x"0000000000000000";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);

--START reading
-- ignore first reading
		EN_RD  <='0';
		wait for (9*PERIOD);
 		EN_RD  <='1';
		wait for (23*PERIOD);





		MAIN_BUS <= x"0000000000000008";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);


  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);


		MAIN_BUS <= x"0000000000000D08";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);


  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);

		MAIN_BUS <= x"0000000000000E08";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);


  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);


		MAIN_BUS <= x"0000000000000F08";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (20*PERIOD);


  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);



















LABEL1:
   for BU in 0 to 10 loop
  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777770";wait for PERIOD;
		MAIN_BUS <= x"0000000000000001";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffff2";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA3";wait for PERIOD;		 
		MAIN_BUS <= x"5555555555555554";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA5";wait for PERIOD;
		MAIN_BUS <= x"5555555555555556";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAA7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
  		wait for (23*PERIOD);

  
  		EN_WR  <='0';
		MAIN_BUS <= x"7777777777777778";wait for PERIOD;
		MAIN_BUS <= x"0000000000000009";wait for PERIOD;
		MAIN_BUS <= x"fffffffffffffffa";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAAb";wait for PERIOD;		 
		MAIN_BUS <= x"555555555555555c";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAAd";wait for PERIOD;
		MAIN_BUS <= x"555555555555555e";wait for PERIOD;
		MAIN_BUS <= x"AAAAAAAAAAAAAAAf";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
		wait for (23*PERIOD);




  		EN_WR  <='0';
		MAIN_BUS <= x"A0000000000000b0";wait for PERIOD;
		MAIN_BUS <= x"B1111111111111b1";wait for PERIOD;
		MAIN_BUS <= x"C2222222222222b2";wait for PERIOD;
		MAIN_BUS <= x"D3333333333333b3";wait for PERIOD;		 
		MAIN_BUS <= x"E4444444444444b4";wait for PERIOD;
		MAIN_BUS <= x"F5555555555555b5";wait for PERIOD;
		MAIN_BUS <= x"A6666666666666b6";wait for PERIOD;
		MAIN_BUS <= x"B7777777777777b7";wait for PERIOD;		 

		MAIN_BUS  <= (others=>'Z');
		wait for PERIOD;
		EN_WR  <='1';		 
		wait for (23*PERIOD);
end loop;



		wait for (6*PERIOD);
		wait for (25*PERIOD);						




		MAIN_BUS <= x"0000000000000000";
		set_addr <= '0';
		wait for PERIOD;
		set_addr <= '1';
		MAIN_BUS  <= (others=>'Z');
		wait for (40*PERIOD);

LABEL2:
  for BUB in 0 to 25 loop

--START reading
-- ignore first reading
		EN_RD  <='0';
		wait for (9*PERIOD);
 		EN_RD  <='1';
		wait for (23*PERIOD);

		EN_RD  <='0';
   	wait for (9*PERIOD);
		EN_RD  <='1';
		wait for (23*PERIOD);

		EN_RD  <='0';
      wait for (9*PERIOD);
      EN_RD  <='1';
      wait for (23*PERIOD);

		EN_RD  <='0';
   	wait for (9*PERIOD);
		EN_RD  <='1';
		wait for (23*PERIOD);

end loop;

--  ****************************************************************
	wait for (25*PERIOD);
	POWERGOOD    <='0';

        wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***




www: process
begin 
u_clk <= '1';
wait for HALF_PERIOD;
u_clk <= '0';
wait for HALF_PERIOD;
end process www;


www33: process (ddr_clk)
begin 
if (rising_edge(ddr_clk)) then

		ddr_casb <= ddr_casbr after 5 ns;
		ddr_cke <= ddr_cker   after 5 ns;
		ddr_rasb <= ddr_rasbr after 5 ns;
		ddr_web <= ddr_webr   after 5 ns;
		ddr_ad <= ddr_adr     after 5 ns;
		ddr_ba <= ddr_bar     after 5 ns;
end if;

end process www33;



END;