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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity counter is
    generic ( bus_width	 : integer := 32);

	 Port ( rst : in std_logic;
           clk : in std_logic;
           count_out : out std_logic_vector(bus_width-1 downto 0));
end counter;

architecture Behavioral of counter is 
  signal count_sig: std_logic_vector(bus_width-1 downto 0);
begin
 
 COUNT: process(rst,clk)
 begin
   if(rst='1')
	then
	  count_sig <= (others=> '0');
	elsif(rising_edge(clk))
	then
	  count_sig <=  count_sig + 1 ;		  
	end if;
 end process;	

 count_out  <=  count_sig;

end Behavioral;