---

clk_0

clock_source v9.1

Parameters clockFrequency 75000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cpu_0

altera_nios2 v9.1

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave onchip_memory2_0.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Fast icache_size _2048 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave onchip_memory2_0.s1 exceptionOffset 32 debug_triggerArming true debug_level Level2 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _0 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false cpuReset false cpuID 0 clockFrequency 75000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 75000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 2048 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x9040020 RESET_ADDR 0x9040000 BREAK_ADDR 0x9080820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 28 DATA_ADDR_WIDTH 28 NUM_OF_SHADOW_REG_SETS 0

---

pio_0

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 75000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 75000000u

---

onchip_memory2_0

altera_avalon_onchip_memory2 v9.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 deviceFamily Cyclone III dualPort false initMemContent true initializationFileName onchip_memory2_0 instanceID NONE memorySize 262144 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "onchip_memory2_0" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 0 SIZE_VALUE 262144u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

---

jtag_uart_0

altera_avalon_jtag_uart v9.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

---

sgdma_0

altera_avalon_sgdma v9.1

Parameters actualDataTransferFIFODepth 64 addressWidth 32 alwaysDoMaxBurst true dataTransferFIFODepth 2 enableBurstTransfers false enableDescriptorReadMasterBurst false enableUnalignedTransfers false internalFIFODepth 2 readBlockDataWidth 32 readBurstcountWidth 4 sinkErrorWidth 0 sourceErrorWidth 1 transferMode MEMORY_TO_STREAM writeBurstcountWidth 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_BLOCK_DATA_WIDTH 32 WRITE_BLOCK_DATA_WIDTH 32 STREAM_DATA_WIDTH 32 ADDRESS_WIDTH 32 HAS_READ_BLOCK 1 HAS_WRITE_BLOCK 0 READ_BURSTCOUNT_WIDTH 4 WRITE_BURSTCOUNT_WIDTH 4 BURST_TRANSFER 0 ALWAYS_DO_MAX_BURST 1 DESCRIPTOR_READ_BURST 0 UNALIGNED_TRANSFER 0 CONTROL_SLAVE_DATA_WIDTH 32 CONTROL_SLAVE_ADDRESS_WIDTH 4 DESC_DATA_WIDTH 32 CHAIN_WRITEBACK_DATA_WIDTH 32 STATUS_TOKEN_DATA_WIDTH 24 BYTES_TO_TRANSFER_DATA_WIDTH 16 BURST_DATA_WIDTH 8 CONTROL_DATA_WIDTH 8 ATLANTIC_CHANNEL_DATA_WIDTH 4 COMMAND_FIFO_DATA_WIDTH 104 SYMBOLS_PER_BEAT 4 IN_ERROR_WIDTH 0 OUT_ERROR_WIDTH 1

---

triple_speed_ethernet_0

triple_speed_ethernet v9.1

Parameters atlanticSinkClockRate 0 atlanticSinkClockSource unassigned atlanticSourceClockRate 0 atlanticSourceClockSource unassigned avalonSlaveClockRate 0 avalonSlaveClockSource unassigned avalonStNeighbours {TRANSMIT=sgdma_0, RECEIVE=sgdma_1} channel_count 1 core_variation MAC_ONLY core_version 2305 crc32check16bit 0 crc32dwidth 8 crc32gendelay 6 crc32s1l2_extern false cust_version 0 dataBitsPerSymbol 8 dev_version 2305 deviceFamily CYCLONEIII eg_addr 11 eg_fifo 2048 ena_hash false enable_alt_reconfig false enable_clk_sharing false enable_ena 32 enable_fifoless false enable_gmii_loopback false enable_hd_logic false enable_mac_flow_ctrl false enable_mac_txaddr_set true enable_mac_vlan false enable_maclite false enable_magic_detect false enable_multi_channel false enable_pkt_class true enable_pma false enable_reg_sharing false enable_sgmii false enable_shift16 false enable_sup_addr false enable_use_internal_fifo true export_calblkclk false export_pwrdn false ext_stat_cnt_ena false gigeAdvanceMode true ifGMII RGMII ifPCSuseEmbeddedSerdes false ing_addr 11 ing_fifo 2048 insert_ta true maclite_gige false max_channels 1 mdio_clk_div 40 phy_identifier 0 ramType AUTO reset_level 1 sopcSystemTopLevelName nios_test1 stat_cnt_ena false timingAdapterName timingAdapter toolContext SOPC_BUILDER transceiver_type GXB uiEgFIFOSize 2048 x 32 Bits uiHostClockFrequency 0 uiIngFIFOSize 2048 x 32 Bits uiMACFIFO false uiMACOptions false uiMDIOFreq 0.0 MHz uiMIIInterfaceOptions false uiPCSInterface false uiPCSInterfaceOptions false useLvds false useMAC true useMDIO true usePCS false use_sync_reset false generateLegacySim false

  

Software Assignments TRANSMIT "sgdma_0" RECEIVE "sgdma_1" TRANSMIT_FIFO_DEPTH 2048 RECEIVE_FIFO_DEPTH 2048 FIFO_WIDTH 32 ENABLE_MACLITE 0 MACLITE_GIGE 0 USE_MDIO 1 NUMBER_OF_CHANNEL 1 NUMBER_OF_MAC_MDIO_SHARED 1 IS_MULTICHANNEL_MAC 0 MDIO_SHARED 0 REGISTER_SHARED 0 PCS 0 PCS_SGMII 0 PCS_ID 0u

---

sgdma_1

altera_avalon_sgdma v9.1

Parameters actualDataTransferFIFODepth 64 addressWidth 32 alwaysDoMaxBurst true dataTransferFIFODepth 2 enableBurstTransfers false enableDescriptorReadMasterBurst false enableUnalignedTransfers false internalFIFODepth 2 readBlockDataWidth 32 readBurstcountWidth 4 sinkErrorWidth 6 sourceErrorWidth 0 transferMode STREAM_TO_MEMORY writeBurstcountWidth 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_BLOCK_DATA_WIDTH 32 WRITE_BLOCK_DATA_WIDTH 32 STREAM_DATA_WIDTH 32 ADDRESS_WIDTH 32 HAS_READ_BLOCK 0 HAS_WRITE_BLOCK 1 READ_BURSTCOUNT_WIDTH 4 WRITE_BURSTCOUNT_WIDTH 4 BURST_TRANSFER 0 ALWAYS_DO_MAX_BURST 1 DESCRIPTOR_READ_BURST 0 UNALIGNED_TRANSFER 0 CONTROL_SLAVE_DATA_WIDTH 32 CONTROL_SLAVE_ADDRESS_WIDTH 4 DESC_DATA_WIDTH 32 CHAIN_WRITEBACK_DATA_WIDTH 32 STATUS_TOKEN_DATA_WIDTH 24 BYTES_TO_TRANSFER_DATA_WIDTH 16 BURST_DATA_WIDTH 8 CONTROL_DATA_WIDTH 8 ATLANTIC_CHANNEL_DATA_WIDTH 4 COMMAND_FIFO_DATA_WIDTH 104 SYMBOLS_PER_BEAT 4 IN_ERROR_WIDTH 6 OUT_ERROR_WIDTH 0

---

tri_state_bridge_0

altera_avalon_tri_state_bridge v9.1

Parameters registerIncomingSignals true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

timer_0

altera_avalon_timer v9.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 100 periodUnits USEC resetOutput false snapshot true systemFrequency 75000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 100 PERIOD_UNITS "us" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 75000000u LOAD_VALUE 7499ULL COUNTER_SIZE 32 MULT 1.0E-6 TICKS_PER_SEC 10000u

---

uart_0

altera_avalon_uart v9.1

Parameters baud 9600 baudError 0.01 clockRate 75000000 dataBits 8 fixedBaud false parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 9600 DATA_BITS 8 FIXED_BAUD 0 PARITY 'N' STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0 SIM_TRUE_BAUD 0 SIM_CHAR_STREAM "" FREQ 75000000u

---

sram32_component_0

sram32_component v1.0

Parameters AUTO_CLOCK_CLOCK_RATE 75000000 sharedPorts ,s0/ats_s0_data deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

sgdma_mem_to_mem

altera_avalon_sgdma v9.1

Parameters actualDataTransferFIFODepth 64 addressWidth 32 alwaysDoMaxBurst true dataTransferFIFODepth 2 enableBurstTransfers true enableDescriptorReadMasterBurst false enableUnalignedTransfers false internalFIFODepth 2 readBlockDataWidth 32 readBurstcountWidth 4 sinkErrorWidth 0 sourceErrorWidth 0 transferMode MEMORY_TO_MEMORY writeBurstcountWidth 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_BLOCK_DATA_WIDTH 32 WRITE_BLOCK_DATA_WIDTH 32 STREAM_DATA_WIDTH 32 ADDRESS_WIDTH 32 HAS_READ_BLOCK 1 HAS_WRITE_BLOCK 1 READ_BURSTCOUNT_WIDTH 4 WRITE_BURSTCOUNT_WIDTH 4 BURST_TRANSFER 1 ALWAYS_DO_MAX_BURST 1 DESCRIPTOR_READ_BURST 0 UNALIGNED_TRANSFER 0 CONTROL_SLAVE_DATA_WIDTH 32 CONTROL_SLAVE_ADDRESS_WIDTH 4 DESC_DATA_WIDTH 32 CHAIN_WRITEBACK_DATA_WIDTH 32 STATUS_TOKEN_DATA_WIDTH 24 BYTES_TO_TRANSFER_DATA_WIDTH 16 BURST_DATA_WIDTH 8 CONTROL_DATA_WIDTH 8 ATLANTIC_CHANNEL_DATA_WIDTH 4 COMMAND_FIFO_DATA_WIDTH 104 IN_ERROR_WIDTH 0 OUT_ERROR_WIDTH 0

---

cfi_flash_0

altera_avalon_cfi_flash v9.1

Parameters actualHoldTime 80.0 actualSetupTime 53.333333333333336 actualWaitTime 133.33333333333334 addressWidth 25 clockRate 75000000 corePreset CUSTOM dataWidth 16 holdTime 6 setupTime 4 sharedPorts s1/data timingUnits CYCLES waitTime 10 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments SETUP_VALUE 4 WAIT_VALUE 10 HOLD_VALUE 6 TIMING_UNITS "cycles" SIZE 67108864u