// designed by Sergey Suslov
//
// pipelined integer divider with reminder correction implemented as an array of sequential divider
// takes in 2 arguments of adjustable width (parameters op_A_width, op_B_width)
// and divide the first one by the second treating them either signed or unsigned depending on op-type input
// with initial latency of op_A_width+1 clock cycles + 1 cycle for reminder correction, provided that stall_n signal is deasserted
// rdy_n output indicates completion of operation with result(rez) and reminder containing valid results
// the unit provides additionally an overflow and division by zero exception flags

//`include "definitions.v"
//`ifndef SYNTHESYS
//  timeunit `verification_time_unit;
//  timeprecision `verification_time_resolution;
//`endif

module division_pipelined 
                          #(
                            parameter op_A_width=16,
                            parameter op_B_width=op_A_width
                          )
                          (
                            input   bit clk,
                            input   bit reset_n, // operands loading
                            input   bit op_type, // 1-signed, 0-unsigned
                            input   bit[op_A_width-1:0] op_A,
                            input   bit[op_B_width-1:0] op_B,
                            output  bit [op_A_width-1:0] rez,
                            output  bit [op_B_width-1:0] remainder,
                            output  bit overflow,
                            output  bit exception_div_by_zero,
                            output  bit rdy_n,
                            input   bit stall_n
                          );

localparam number_of_processing_elements=op_A_width+4;
localparam initial_delay_counter_width=$clog2(op_A_width+4); //

wire [op_A_width-1:0]rez_array[number_of_processing_elements-1:0];
wire [op_B_width-1:0]remainder_array[number_of_processing_elements-1:0];
wire [number_of_processing_elements-1:0]overflow_array;
wire [number_of_processing_elements-1:0]exception_div_by_zero_array;
wire [number_of_processing_elements-1:0]rdy_n_array;
reg [number_of_processing_elements-1:0] load_signal_array;
reg [initial_delay_counter_width-1:0]initial_delay_counter;

generate 
	genvar i;
	for (i=0;i<number_of_processing_elements;i=i+1)
		begin: divider_array
			div_signed_unsigned #(.op_A_width(op_A_width),.op_B_width(op_B_width)) divider_element (clk, ~load_signal_array[i], op_type, op_A, op_B, rez_array[i], remainder_array[i], overflow_array[i], exception_div_by_zero_array[i], rdy_n_array[i], stall_n);
		end
endgenerate

always_ff @(posedge clk)
	begin
		if (~reset_n)
			begin
				load_signal_array<=1;
				initial_delay_counter<=number_of_processing_elements;
			end
		else
			begin
				if (stall_n==1)
					begin
						load_signal_array[number_of_processing_elements-1:0+1]<=load_signal_array[number_of_processing_elements-1-1:0];
						load_signal_array[0]<=load_signal_array[number_of_processing_elements-1];
						if (initial_delay_counter!=0)initial_delay_counter<=initial_delay_counter-1;
					end
			end
	end

always_comb
	begin
	 for (int j=0;j<number_of_processing_elements;j=j+1)
	 	begin
	 		if (load_signal_array[j]==1)
	 			begin
					rez=rez_array[j];
					remainder=remainder_array[j];
					overflow=overflow_array[j];
					exception_div_by_zero=exception_div_by_zero_array[j];
					if (initial_delay_counter==0)rdy_n=rdy_n_array[j];
						else rdy_n=1'b1;
	 			end
	 	end
	end

endmodule