Warning: Using design file Video2Ethernet.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: Video2Ethernet Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(127): created implicit net for "jtag_debug_offchip_trace_clk_from_the_cpu_0" Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(128): created implicit net for "jtag_debug_offchip_trace_data_from_the_cpu_0" Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(129): created implicit net for "jtag_debug_trigout_from_the_cpu_0" Warning (10034): Output port "jtag_debug_offchip_trace_clk_from_the_cpu" at Video2Ethernet.v(39) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[17]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[16]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[15]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[14]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[13]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[12]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[11]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[10]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[9]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[8]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[7]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[6]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[5]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[4]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[3]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[2]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[1]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[0]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_trigout_from_the_cpu" at Video2Ethernet.v(41) has no driver Warning: Using design file V2E_system.v, which is not specified as a design file for the current project, but contains definitions for 22 design units and 22 entities in project Info: Found entity 1: BT_decoder_avalon_slave_0_arbitrator Info: Found entity 2: V2E_system_clock_0_in_arbitrator Info: Found entity 3: V2E_system_clock_0_out_arbitrator Info: Found entity 4: cpu_0_jtag_debug_module_arbitrator Info: Found entity 5: cpu_0_data_master_arbitrator Info: Found entity 6: cpu_0_instruction_master_arbitrator Info: Found entity 7: rdv_fifo_for_cpu_0_data_master_to_ddr_sdram_0_s1_module Info: Found entity 8: rdv_fifo_for_cpu_0_instruction_master_to_ddr_sdram_0_s1_module Info: Found entity 9: rdv_fifo_for_dma_read_master_to_ddr_sdram_0_s1_module Info: Found entity 10: ddr_sdram_0_s1_arbitrator Info: Found entity 11: dma_control_port_slave_arbitrator Info: Found entity 12: dma_read_master_arbitrator Info: Found entity 13: dma_write_master_arbitrator Info: Found entity 14: high_res_timer_s1_arbitrator Info: Found entity 15: jtag_uart_avalon_jtag_slave_arbitrator Info: Found entity 16: opencores_i2c_master_s1_arbitrator Info: Found entity 17: performance_counter_control_slave_arbitrator Info: Found entity 18: pio_leds_s1_arbitrator Info: Found entity 19: pll_s1_arbitrator Info: Found entity 20: V2E_system_reset_pll_c0_out_domain_synch_module Info: Found entity 21: V2E_system_reset_clk_domain_synch_module Info: Found entity 22: V2E_system Warning (10036): Verilog HDL or VHDL warning at test_BT_decoder.v(38): object "linecntr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(45): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(46): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(47): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(71): truncated value with size 32 to match size of target (11) Warning (10240): Verilog HDL Always Construct warning at test_BT_decoder.v(58): inferring latch(es) for variable "ptr1", which holds its previous value in one or more paths through the always construct Warning (10034): Output port "leds[7]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[6]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[5]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[4]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[3]" at test_BT_decoder.v(28) has no driver Warning: Using design file V2E_system_clock_0.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project Info: Found entity 1: V2E_system_clock_0_edge_to_pulse Info: Found entity 2: V2E_system_clock_0_slave_FSM Info: Found entity 3: V2E_system_clock_0_master_FSM Info: Found entity 4: V2E_system_clock_0_bit_pipe Info: Found entity 5: V2E_system_clock_0 Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_test_bench Warning: Using design file cpu_0_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_mult_cell Warning: Using design file cpu_0_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_oci_test_bench Warning: Entity "cpu_0_oci_test_bench" contains only dangling pins Warning: Using design file cpu_0_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_wrapper Warning: Using design file cpu_0_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_tck Warning: Using design file cpu_0_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_sysclk Warning: Using design file cpu_0_ext_trace_pll_module.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_ext_trace_pll_module Warning: Using design file ddr_sdram_0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0 Warning: Using design file ddr_sdram_0_auk_ddr_sdram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_sdram Warning: Using design file ddr_sdram_0_auk_ddr_datapath.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_datapath Warning: Using design file ddr_sdram_0_auk_ddr_clk_gen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_clk_gen Warning: Using design file ddr_sdram_0_auk_ddr_dqs_group.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_dqs_group Warning: Using design file dma.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project Info: Found entity 1: dma_read_data_mux Info: Found entity 2: dma_byteenables Info: Found entity 3: dma_fifo_module_fifo_ram_module Info: Found entity 4: dma_fifo_module Info: Found entity 5: dma_mem_read Info: Found entity 6: dma_mem_write Info: Found entity 7: dma Warning: Using design file high_res_timer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: high_res_timer Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project Info: Found entity 1: jtag_uart_log_module Info: Found entity 2: jtag_uart_sim_scfifo_w Info: Found entity 3: jtag_uart_scfifo_w Info: Found entity 4: jtag_uart_drom_module Info: Found entity 5: jtag_uart_sim_scfifo_r Info: Found entity 6: jtag_uart_scfifo_r Info: Found entity 7: jtag_uart Warning: Using design file opencores_i2c_master.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: opencores_i2c_master Warning: Using design file oc_i2c_master.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: oc_i2c_master-behavior Info: Found entity 1: oc_i2c_master Warning (10541): VHDL Signal Declaration warning at oc_i2c_master.vhd(17): used implicit default value for signal "wb_err_o" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10873): Using initial value X (don't care) for net "wb_dat_o[31]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[30]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[29]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[28]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[27]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[26]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[25]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[24]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[23]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[22]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[21]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[20]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[19]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[18]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[17]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[16]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[15]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[14]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[13]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[12]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[11]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[10]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[9]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[8]" at oc_i2c_master.vhd(16) Warning: Using design file i2c_master_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_top-structural Info: Found entity 1: i2c_master_top Warning: Using design file i2c_master_byte_ctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_byte_ctrl-structural Info: Found entity 1: i2c_master_byte_ctrl Warning: Using design file i2c_master_bit_ctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_bit_ctrl-structural Info: Found entity 1: i2c_master_bit_ctrl Warning: Using design file performance_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: performance_counter Warning: Using design file pio_leds.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: pio_leds Warning: Using design file pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: pll Warning: Using design file altpllpll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altpllpll Warning: Using design file ddr_sdram_0_auk_ddr_dll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_dll Warning: Hierarchy name "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst" does not exist. It is associated with user assignments. Warning: Hierarchy name "ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component" does not exist. It is associated with user assignments. Warning: Messages from megafunction that supports OpenCore Plus feature Warning: Messages from megafunction that supports OpenCore Plus feature DDR SDRAM Controller Warning: The local_ready output will go low when the evaluation time expires Warning: Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed Warning: 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning: Using design file Video2Ethernet.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: Video2Ethernet Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(127): created implicit net for "jtag_debug_offchip_trace_clk_from_the_cpu_0" Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(128): created implicit net for "jtag_debug_offchip_trace_data_from_the_cpu_0" Warning (10236): Verilog HDL Implicit Net warning at Video2Ethernet.v(129): created implicit net for "jtag_debug_trigout_from_the_cpu_0" Warning (10034): Output port "jtag_debug_offchip_trace_clk_from_the_cpu" at Video2Ethernet.v(39) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[17]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[16]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[15]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[14]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[13]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[12]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[11]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[10]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[9]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[8]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[7]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[6]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[5]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[4]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[3]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[2]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[1]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_offchip_trace_data_from_the_cpu[0]" at Video2Ethernet.v(40) has no driver Warning (10034): Output port "jtag_debug_trigout_from_the_cpu" at Video2Ethernet.v(41) has no driver Warning: Using design file V2E_system.v, which is not specified as a design file for the current project, but contains definitions for 22 design units and 22 entities in project Info: Found entity 1: BT_decoder_avalon_slave_0_arbitrator Info: Found entity 2: V2E_system_clock_0_in_arbitrator Info: Found entity 3: V2E_system_clock_0_out_arbitrator Info: Found entity 4: cpu_0_jtag_debug_module_arbitrator Info: Found entity 5: cpu_0_data_master_arbitrator Info: Found entity 6: cpu_0_instruction_master_arbitrator Info: Found entity 7: rdv_fifo_for_cpu_0_data_master_to_ddr_sdram_0_s1_module Info: Found entity 8: rdv_fifo_for_cpu_0_instruction_master_to_ddr_sdram_0_s1_module Info: Found entity 9: rdv_fifo_for_dma_read_master_to_ddr_sdram_0_s1_module Info: Found entity 10: ddr_sdram_0_s1_arbitrator Info: Found entity 11: dma_control_port_slave_arbitrator Info: Found entity 12: dma_read_master_arbitrator Info: Found entity 13: dma_write_master_arbitrator Info: Found entity 14: high_res_timer_s1_arbitrator Info: Found entity 15: jtag_uart_avalon_jtag_slave_arbitrator Info: Found entity 16: opencores_i2c_master_s1_arbitrator Info: Found entity 17: performance_counter_control_slave_arbitrator Info: Found entity 18: pio_leds_s1_arbitrator Info: Found entity 19: pll_s1_arbitrator Info: Found entity 20: V2E_system_reset_pll_c0_out_domain_synch_module Info: Found entity 21: V2E_system_reset_clk_domain_synch_module Info: Found entity 22: V2E_system Warning (10036): Verilog HDL or VHDL warning at test_BT_decoder.v(38): object "linecntr" assigned a value but never read Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(45): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(46): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(47): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at test_BT_decoder.v(71): truncated value with size 32 to match size of target (11) Warning (10240): Verilog HDL Always Construct warning at test_BT_decoder.v(58): inferring latch(es) for variable "ptr1", which holds its previous value in one or more paths through the always construct Warning (10034): Output port "leds[7]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[6]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[5]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[4]" at test_BT_decoder.v(28) has no driver Warning (10034): Output port "leds[3]" at test_BT_decoder.v(28) has no driver Warning: Using design file V2E_system_clock_0.v, which is not specified as a design file for the current project, but contains definitions for 5 design units and 5 entities in project Info: Found entity 1: V2E_system_clock_0_edge_to_pulse Info: Found entity 2: V2E_system_clock_0_slave_FSM Info: Found entity 3: V2E_system_clock_0_master_FSM Info: Found entity 4: V2E_system_clock_0_bit_pipe Info: Found entity 5: V2E_system_clock_0 Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_test_bench Warning: Using design file cpu_0_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_mult_cell Warning: Using design file cpu_0_oci_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_oci_test_bench Warning: Entity "cpu_0_oci_test_bench" contains only dangling pins Warning: Using design file cpu_0_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_wrapper Warning: Using design file cpu_0_jtag_debug_module_tck.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_tck Warning: Using design file cpu_0_jtag_debug_module_sysclk.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_jtag_debug_module_sysclk Warning: Using design file cpu_0_ext_trace_pll_module.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: cpu_0_ext_trace_pll_module Warning: Using design file ddr_sdram_0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0 Warning: Using design file ddr_sdram_0_auk_ddr_sdram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_sdram Warning: Using design file ddr_sdram_0_auk_ddr_datapath.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_datapath Warning: Using design file ddr_sdram_0_auk_ddr_clk_gen.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_clk_gen Warning: Using design file ddr_sdram_0_auk_ddr_dqs_group.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_dqs_group Warning: Using design file dma.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project Info: Found entity 1: dma_read_data_mux Info: Found entity 2: dma_byteenables Info: Found entity 3: dma_fifo_module_fifo_ram_module Info: Found entity 4: dma_fifo_module Info: Found entity 5: dma_mem_read Info: Found entity 6: dma_mem_write Info: Found entity 7: dma Warning: Using design file high_res_timer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: high_res_timer Warning: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project Info: Found entity 1: jtag_uart_log_module Info: Found entity 2: jtag_uart_sim_scfifo_w Info: Found entity 3: jtag_uart_scfifo_w Info: Found entity 4: jtag_uart_drom_module Info: Found entity 5: jtag_uart_sim_scfifo_r Info: Found entity 6: jtag_uart_scfifo_r Info: Found entity 7: jtag_uart Warning: Using design file opencores_i2c_master.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: opencores_i2c_master Warning: Using design file oc_i2c_master.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: oc_i2c_master-behavior Info: Found entity 1: oc_i2c_master Warning (10541): VHDL Signal Declaration warning at oc_i2c_master.vhd(17): used implicit default value for signal "wb_err_o" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning (10873): Using initial value X (don't care) for net "wb_dat_o[31]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[30]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[29]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[28]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[27]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[26]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[25]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[24]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[23]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[22]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[21]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[20]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[19]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[18]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[17]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[16]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[15]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[14]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[13]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[12]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[11]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[10]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[9]" at oc_i2c_master.vhd(16) Warning (10873): Using initial value X (don't care) for net "wb_dat_o[8]" at oc_i2c_master.vhd(16) Warning: Using design file i2c_master_top.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_top-structural Info: Found entity 1: i2c_master_top Warning: Using design file i2c_master_byte_ctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_byte_ctrl-structural Info: Found entity 1: i2c_master_byte_ctrl Warning: Using design file i2c_master_bit_ctrl.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: i2c_master_bit_ctrl-structural Info: Found entity 1: i2c_master_bit_ctrl Warning: Using design file performance_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: performance_counter Warning: Using design file pio_leds.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: pio_leds Warning: Using design file pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: pll Warning: Using design file altpllpll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: altpllpll Warning: Using design file ddr_sdram_0_auk_ddr_dll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: ddr_sdram_0_auk_ddr_dll Warning: Synthesized away the following node(s): Warning: Synthesized away the following PLL node(s): Warning (14320): Synthesized away node "V2E_system:V2E_system_inst|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_ext_trace_pll_module:the_cpu_0_ext_trace_pll_module|altclklock:cpu_0_nios2_oci_altclklock|altpll:pll|pll" Warning: OpenCore Plus Hardware Evaluation feature is turned on for the following cores Warning: ""DDR SDRAM Controller" (6AF7_0055)" will use the OpenCore Plus Hardware Evaluation feature Warning: Messages from megafunction that supports OpenCore Plus feature Warning: Messages from megafunction that supports OpenCore Plus feature DDR SDRAM Controller Warning: The local_ready output will go low when the evaluation time expires Warning: Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed Warning: 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder Warning: Open-drain buffer(s) that do not directly drive top-level pin(s) are removed Warning: Converted the fanout from the open-drain buffer "V2E_system:V2E_system_inst|opencores_i2c_master:the_opencores_i2c_master|oc_i2c_master:the_oc_i2c_master|scl_pad_io" to the node "V2E_system:V2E_system_inst|opencores_i2c_master:the_opencores_i2c_master|oc_i2c_master:the_oc_i2c_master|i2c_master_top:i2c_top_inst|i2c_master_byte_ctrl:u1|i2c_master_bit_ctrl:u1|sSCL" into a wire Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "jtag_debug_offchip_trace_clk_from_the_cpu" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[0]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[1]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[2]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[3]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[4]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[5]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[6]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[7]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[8]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[9]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[10]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[11]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[12]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[13]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[14]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[15]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[16]" is stuck at GND Warning (13410): Pin "jtag_debug_offchip_trace_data_from_the_cpu[17]" is stuck at GND Warning (13410): Pin "jtag_debug_trigout_from_the_cpu" is stuck at GND Warning (13410): Pin "clk_to_sdram[1]" is stuck at GND Warning (13410): Pin "clk_to_sdram_n[1]" is stuck at GND Warning (13410): Pin "ddr_cas_n[1]" is stuck at GND Warning (13410): Pin "ddr_cke[1]" is stuck at GND Warning (13410): Pin "ddr_cs_n[1]" is stuck at GND Warning (13410): Pin "ddr_ras_n[1]" is stuck at GND Warning (13410): Pin "ddr_we_n[1]" is stuck at GND Warning (13410): Pin "out_port_from_the_led_pio_fk[3]" is stuck at GND Warning (13410): Pin "out_port_from_the_led_pio_fk[4]" is stuck at GND Warning (13410): Pin "out_port_from_the_led_pio_fk[5]" is stuck at GND Warning (13410): Pin "out_port_from_the_led_pio_fk[6]" is stuck at GND Warning (13410): Pin "out_port_from_the_led_pio_fk[7]" is stuck at GND Warning: Ignored 5 Virtual Pin logic option assignments Warning: Ignored Virtual Pin assignment to "pll_c0_domain_reset". Warning: Ignored Virtual Pin assignment to "ext_ssram_bus_address[0]". Warning: Ignored Virtual Pin assignment to "ext_ssram_bus_address[1]". Warning: Ignored Virtual Pin assignment to "pll_c0_domain". Warning: Ignored Virtual Pin assignment to "reset_to_the_lan91c111". Warning: Design contains 11 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "Y[0]" Warning (15610): No output dependent on input pin "Y[1]" Warning (15610): No output dependent on input pin "Y[2]" Warning (15610): No output dependent on input pin "Y[3]" Warning (15610): No output dependent on input pin "Y[4]" Warning (15610): No output dependent on input pin "Y[5]" Warning (15610): No output dependent on input pin "Y[6]" Warning (15610): No output dependent on input pin "Y[7]" Warning (15610): No output dependent on input pin "Y[8]" Warning (15610): No output dependent on input pin "Y[9]" Warning (15610): No output dependent on input pin "in_port_to_the_button_pio[1]" Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Warning: Ignored I/O standard assignments to the following nodes Warning: Ignored I/O standard assignment to node "C[0]" Warning: Ignored I/O standard assignment to node "C[1]" Warning: Ignored I/O standard assignment to node "C[2]" Warning: Ignored I/O standard assignment to node "C[3]" Warning: Ignored I/O standard assignment to node "C[4]" Warning: Ignored I/O standard assignment to node "C[5]" Warning: Ignored I/O standard assignment to node "C[6]" Warning: Ignored I/O standard assignment to node "C[7]" Warning: Ignored I/O standard assignment to node "C[8]" Warning: Ignored I/O standard assignment to node "C[9]" Warning: Ignored I/O standard assignment to node "FID_GPIO" Warning: Ignored I/O standard assignment to node "GLCO_I2CA" Warning: Ignored I/O standard assignment to node "HS_CS_GPIO" Warning: Ignored I/O standard assignment to node "INTREQ" Warning: Ignored I/O standard assignment to node "VS_VBLK_GPIO" Warning: Ignored I/O standard assignment to node "clock_source" Warning: Ignored locations or region assignments to the following nodes Warning: Node "C[0]" is assigned to location or region, but does not exist in design Warning: Node "C[1]" is assigned to location or region, but does not exist in design Warning: Node "C[2]" is assigned to location or region, but does not exist in design Warning: Node "C[3]" is assigned to location or region, but does not exist in design Warning: Node "C[4]" is assigned to location or region, but does not exist in design Warning: Node "C[5]" is assigned to location or region, but does not exist in design Warning: Node "C[6]" is assigned to location or region, but does not exist in design Warning: Node "C[7]" is assigned to location or region, but does not exist in design Warning: Node "C[8]" is assigned to location or region, but does not exist in design Warning: Node "C[9]" is assigned to location or region, but does not exist in design Warning: Node "FID_GPIO" is assigned to location or region, but does not exist in design Warning: Node "GLCO_I2CA" is assigned to location or region, but does not exist in design Warning: Node "HS_CS_GPIO" is assigned to location or region, but does not exist in design Warning: Node "INTREQ" is assigned to location or region, but does not exist in design Warning: Node "PROTO1_IO[40]" is assigned to location or region, but does not exist in design Warning: Node "VS_VBLK_GPIO" is assigned to location or region, but does not exist in design Warning: Node "bidir_port_to_and_from_the_reconfig_request_pio" is assigned to location or region, but does not exist in design Warning: Node "enet_ads_n" is assigned to location or region, but does not exist in design Warning: Node "enet_aen" is assigned to location or region, but does not exist in design Warning: Node "in_port_to_the_button_pio[2]" is assigned to location or region, but does not exist in design Warning: Node "in_port_to_the_button_pio[3]" is assigned to location or region, but does not exist in design Warning: Node "pll_c0_out" is assigned to location or region, but does not exist in design Warning: Found 39 output pins without output pin load capacitance assignment Info: Pin "SCL_PAD_IO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "SDA_PAD_IO" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "pll_c1_out" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_clk_from_the_cpu" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_offchip_trace_data_from_the_cpu[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "jtag_debug_trigout_from_the_cpu" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_n[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Info: Pin "out_port_from_the_led_pio_fk[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Following 29 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin jtag_debug_offchip_trace_clk_from_the_cpu has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[0] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[1] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[2] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[3] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[4] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[5] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[6] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[7] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[8] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[9] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[10] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[11] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[12] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[13] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[14] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[15] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[16] has GND driving its datain port Info: Pin jtag_debug_offchip_trace_data_from_the_cpu[17] has GND driving its datain port Info: Pin jtag_debug_trigout_from_the_cpu has GND driving its datain port Info: Pin out_port_from_the_led_pio_fk[3] has GND driving its datain port Info: Pin out_port_from_the_led_pio_fk[4] has GND driving its datain port Info: Pin out_port_from_the_led_pio_fk[5] has GND driving its datain port Info: Pin out_port_from_the_led_pio_fk[6] has GND driving its datain port Info: Pin out_port_from_the_led_pio_fk[7] has GND driving its datain port Info: Pin ENET_ADS_N has GND driving its datain port Info: Pin ENET_AEN has GND driving its datain port Info: Pin ssram_adsp_n has VCC driving its datain port Info: Pin ssram_adv_n has VCC driving its datain port Warning: Can't convert time-limited SOF into POF, HEX File, TTF, or RBF Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled Warning: Found pins functioning as undefined clocks and/or memory enables Info: Assuming node "altera_internal_jtag~TCKUTAP" is an undefined clock Info: Assuming node "altera_internal_jtag~UPDATEUSER" is an undefined clock Info: Assuming node "CLK_FROM_BT656_CARD" is an undefined clock Info: Assuming node "altera_internal_jtag~CLKDRUSER" is an undefined clock Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected gated clock "V2E_system:V2E_system_inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_clk[0]" as buffer Info: Detected ripple clock "V2E_system:V2E_system_inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_io~regout" as buffer Info: Detected gated clock "V2E_system:V2E_system_inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_clk[0]" as buffer Info: Detected ripple clock "V2E_system:V2E_system_inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_io~regout" as buffer Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details