Release 11.4 - xst L.68 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.22 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.22 secs
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc3s4000-5-fg676

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 7
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : top.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : { "ipcore_dir" }

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ipcore_dir/fifo_2048_36.v" in library work
Compiling verilog file "src/other_src/M8_1E.v" in library work
Module <fifo_2048_36> compiled
Compiling verilog file "src/mac_src/mac_rx/mac_rx_ff_write.v" in library work
Module <M8_1E> compiled
Compiling verilog file "src/mac_src/mac_rx/mac_rx_ff_read.v" in library work
Module <mac_rx_ff_write> compiled
Compiling verilog file "ram_8x8_dp.v" in library work
Module <mac_rx_ff_read> compiled
Compiling verilog file "ram_64x32.v" in library work
Module <ram_8x8_dp> compiled
Compiling verilog file "ram_512x36_tx.v" in library work
Module <ram_64x32> compiled
Compiling verilog file "ram_512x36_rx.v" in library work
Module <ram_512x36_tx> compiled
Compiling verilog file "src/other_src/short_impulse.v" in library work
Module <ram_512x36_rx> compiled
Compiling verilog file "src/mac_src/tech/clock_switch.v" in library work
Module <short_impulse> compiled
Compiling verilog file "src/mac_src/tech/clock_div.v" in library work
Module <clock_switch> compiled
Compiling verilog file "src/mac_src/rmon/rmon_dpram.v" in library work
Module <clock_div> compiled
Compiling verilog file "src/mac_src/rmon/rmon_ctrl.v" in library work
Module <rmon_dpram> compiled
Compiling verilog file "src/mac_src/rmon/rmon_addr_gen.v" in library work
Module <rmon_ctrl> compiled
Compiling verilog file "src/mac_src/mac_tx/ramdon_gen.v" in library work
Module <rmon_addr_gen> compiled
Compiling verilog file "src/mac_src/mac_tx/mac_tx_ff.v" in library work
Module <ramdon_gen> compiled
Compiling verilog file "src/mac_src/mac_tx/mac_tx_ctrl.v" in library work
Module <mac_tx_ff> compiled
Compiling verilog file "src/mac_src/mac_tx/mac_tx_addr_add.v" in library work
Module <mac_tx_ctrl> compiled
Compiling verilog file "src/mac_src/mac_tx/flow_ctrl.v" in library work
Module <mac_tx_addr_add> compiled
Compiling verilog file "src/mac_src/mac_tx/crc_gen.v" in library work
Module <flow_ctrl> compiled
Compiling verilog file "src/mac_src/mac_rx/mac_rx_ff_new.v" in library work
Compiling verilog include file "header.v"
Module <crc_gen> compiled
Compiling verilog file "src/mac_src/mac_rx/mac_rx_ctrl.v" in library work
Module <mac_rx_ff_new> compiled
Compiling verilog file "src/mac_src/mac_rx/mac_rx_add_chk.v" in library work
Module <mac_rx_ctrl> compiled
Compiling verilog file "src/mac_src/mac_rx/crc_chk.v" in library work
Module <mac_rx_add_chk> compiled
Compiling verilog file "src/mac_src/mac_rx/broadcast_filter.v" in library work
Module <crc_chk> compiled
Compiling verilog file "src/mac_buf_src/sram_addr_count.v" in library work
Module <broadcast_filter> compiled
Compiling verilog file "src/mac_buf_src/mux_priority.v" in library work
Module <sram_addr_count> compiled
Compiling verilog file "src/bus_src/priority_rd_addr_counter.v" in library work
Module <mux_priority> compiled
Compiling verilog file "src/bus_src/priority_packet_counter.v" in library work
Module <priority_rd_addr_counter> compiled
Compiling verilog file "src/_temp_src/tx_write_fsm.v" in library work
Module <priority_packet_counter> compiled
Compiling verilog file "src/_temp_src/tx_read_fsm.v" in library work
Module <tx_write_fsm> compiled
Compiling verilog file "src/_temp_src/tx_buffer_fsm_new.v" in library work
Module <tx_read_fsm> compiled
Compiling verilog file "src/serdes_src/tx_write.v" in library work
Module <tx_buffer_fsm_new> compiled
Compiling verilog file "src/other_src/one_sfp_irq.v" in library work
Module <tx_write> compiled
Compiling verilog file "src/other_src/one_sfp_als.v" in library work
Module <one_sfp_irq> compiled
Compiling verilog file "src/mac_src/rmon.v" in library work
Module <one_sfp_als> compiled
Compiling verilog file "src/mac_src/regs_int.v" in library work
Module <rmon> compiled
Compiling verilog file "src/mac_src/phy_int_new.v" in library work
Module <regs_int> compiled
Compiling verilog file "src/mac_src/mac_tx.v" in library work
Module <phy_int_new> compiled
Compiling verilog file "src/mac_src/mac_rx.v" in library work
Module <mac_tx> compiled
Compiling verilog file "src/mac_src/clock_ctrl_new.v" in library work
Module <mac_rx> compiled
Compiling verilog file "src/mac_buf_src/rx_write_fsm.v" in library work
Module <clock_ctrl_new> compiled
Compiling verilog file "src/mac_buf_src/rx_read_fsm.v" in library work
Compiling verilog include file "header.v"
Module <rx_write_fsm> compiled
Compiling verilog file "src/bus_src/select_source.v" in library work
Module <rx_read_fsm> compiled
Compiling verilog file "src/bus_src/one_channel_packet_counters.v" in library work
Compiling verilog include file "header.v"
Module <select_source> compiled
Compiling verilog file "sram_read_dcm.v" in library work
Module <one_channel_packet_counters> compiled
Compiling verilog file "fifo_512x36.v" in library work
Module <sram_read_dcm> compiled
Compiling verilog file "src/_temp_src/tx_buffer_new.v" in library work
Module <fifo_512x36> compiled
Compiling verilog file "src/_temp_src/pci_to_mac_fsm.v" in library work
Module <tx_buffer_new> compiled
Compiling verilog file "src/sram_src/sram_write_clock.v" in library work
Module <pci_to_mac_fsm> compiled
Compiling verilog file "src/sram_src/sram_write.v" in library work
Module <sram_write_clock> compiled
Compiling verilog file "src/sram_src/sram_read_new.v" in library work
Module <sram_write> compiled
Compiling verilog file "src/sram_src/sram_read_clock.v" in library work
Module <sram_read_new> compiled
Compiling verilog file "src/sram_src/sram_address.v" in library work
Module <sram_read_clock> compiled
Compiling verilog file "src/serdes_src/tx_ddr.v" in library work
Module <sram_address> compiled
Compiling verilog file "src/serdes_src/rx_ddr.v" in library work
Module <tx_ddr> compiled
Compiling verilog file "src/other_src/sfp_irq.v" in library work
Module <rx_ddr> compiled
Compiling verilog file "src/other_src/sfp_als.v" in library work
Module <sfp_irq> compiled
Compiling verilog file "src/other_src/reset_gen.v" in library work
Module <sfp_als> compiled
Compiling verilog file "src/other_src/mdio_fsm.v" in library work
Module <reset_gen> compiled
Compiling verilog file "input_dcm.v" in library work
Module <mdio_fsm> compiled
Compiling verilog file "src/other_src/iic_state_machine fsm.v" in library work
Module <input_dcm> compiled
Compiling verilog file "src/mac_src/mac_top_new.v" in library work
Module <iic_state_machine> compiled
Compiling verilog file "src/mac_buf_src/rx_buffer_new.v" in library work
Module <mac_top_new> compiled
Compiling verilog file "src/mac_buf_src/port_regs.v" in library work
Module <rx_buffer_new> compiled
Compiling verilog file "src/mac_buf_src/mac_bus_mux.v" in library work
Module <port_regs> compiled
Compiling verilog file "src/bus_src/rx_packet_counters.v" in library work
Compiling verilog include file "header.v"
Module <mac_bus_mux> compiled
Compiling verilog file "src/arbiter_src/sram_write_mux.v" in library work
Module <rx_packet_counters> compiled
Compiling verilog file "src/arbiter_src/sram_read_mux.v" in library work
Module <sram_write_mux> compiled
Compiling verilog file "fifo_16x36.v" in library work
Module <sram_read_mux> compiled
Compiling verilog file "src/_temp_src/mac_mux.v" in library work
Module <fifo_16x36> compiled
Compiling verilog file "src/sram_src/sram_ctrl.v" in library work
Module <mac_mux> compiled
Compiling verilog file "src/serdes_src/serdes.v" in library work
Module <sram_ctrl> compiled
Compiling verilog file "src/other_src/timer.v" in library work
Module <serdes> compiled
Compiling verilog file "src/other_src/spi_to_epc.v" in library work
Module <timer> compiled
Compiling verilog file "src/other_src/sfp.v" in library work
Module <spi_to_epc> compiled
Compiling verilog file "src/other_src/phy_new.v" in library work
Module <sfp> compiled
Compiling verilog file "src/other_src/mdio.v" in library work
Module <phy_new> compiled
Compiling verilog file "src/other_src/clock_gen.v" in library work
Module <mdio> compiled
Compiling verilog file "src/mac_buf_src/mac_and_buf.v" in library work
Module <clock_gen> compiled
Compiling verilog file "src/bus_src/bus.v" in library work
Module <mac_and_buf> compiled
Compiling verilog file "src/arbiter_src/memory_arbiter.v" in library work
Module <bus> compiled
Compiling verilog file "src/top.v" in library work
Module <memory_arbiter> compiled
Module <top> compiled
No errors in compilation
Analysis of file <"top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <top> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <clock_gen> in library <work> with parameters.
	GND = "0"
	PERIOD_OF_MHZ = "1111100"
	VCC = "1"

Analyzing hierarchy for module <spi_to_epc> in library <work> with parameters.
	GND = "0"
	STATE_DATA_RECEIVE = "011"
	STATE_DATA_TRANSMIT = "100"
	STATE_PAUSE = "000"
	STATE_REG_ADDR = "010"
	STATE_SLAVE_ADDR = "001"
	VCC = "1"

Analyzing hierarchy for module <mac_and_buf> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mac_and_buf> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mac_and_buf> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mac_and_buf> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <bus> in library <work> with parameters.
	GND = "0"
	STATE_CHECK = "00"
	STATE_NEXT = "11"
	STATE_READ = "01"
	STATE_READ_PAUSE = "0"
	STATE_READ_READ = "1"
	STATE_WRITE = "10"
	STATE_WRITE_END = "10"
	STATE_WRITE_FINISH = "11"
	STATE_WRITE_PAUSE = "00"
	STATE_WRITE_WRITE = "01"
	VCC = "1"

Analyzing hierarchy for module <serdes> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mac_mux> in library <work>.

Analyzing hierarchy for module <memory_arbiter> in library <work>.

Analyzing hierarchy for module <sram_ctrl> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mdio> in library <work> with parameters.
	ADDR_MDIO_BUSY = "00000101"
	ADDR_MDIO_DATA = "00000100"
	ADDR_MDIO_ERROR = "00000110"
	ADDR_MDIO_OPCODE = "00000001"
	ADDR_MDIO_PHY_ADDR = "00000010"
	ADDR_MDIO_REG_ADDR = "00000011"
	ADDR_MDIO_SEL = "00000000"
	ADDR_MDIO_START = "00000111"

Analyzing hierarchy for module <sfp> in library <work> with parameters.
	ADDR_IIC_BUSY = "00000101"
	ADDR_IIC_DATA = "00000100"
	ADDR_IIC_ERROR = "00000110"
	ADDR_IIC_REG_ADDR = "00000011"
	ADDR_IIC_RW = "00000001"
	ADDR_IIC_SEL = "00000000"
	ADDR_IIC_SLAVE_ADDR = "00000010"
	ADDR_IIC_START = "00000111"
	ADDR_SFP0_ALS_ENABLE = "00001110"
	ADDR_SFP0_LOS = "00001010"
	ADDR_SFP0_MASK = "00001101"
	ADDR_SFP0_PRESENT = "00001100"
	ADDR_SFP0_RATE_SEL = "00001011"
	ADDR_SFP0_TX_DISABLE = "00001000"
	ADDR_SFP0_TX_FAULT = "00001001"
	ADDR_SFP1_ALS_ENABLE = "00010110"
	ADDR_SFP1_LOS = "00010010"
	ADDR_SFP1_MASK = "00010101"
	ADDR_SFP1_PRESENT = "00010100"
	ADDR_SFP1_RATE_SEL = "00010011"
	ADDR_SFP1_TX_DISABLE = "00010000"
	ADDR_SFP1_TX_FAULT = "00010001"
	ADDR_SFP2_ALS_ENABLE = "00011110"
	ADDR_SFP2_LOS = "00011010"
	ADDR_SFP2_MASK = "00011101"
	ADDR_SFP2_PRESENT = "00011100"
	ADDR_SFP2_RATE_SEL = "00011011"
	ADDR_SFP2_TX_DISABLE = "00011000"
	ADDR_SFP2_TX_FAULT = "00011001"
	ADDR_SFP3_ALS_ENABLE = "00100110"
	ADDR_SFP3_LOS = "00100010"
	ADDR_SFP3_MASK = "00100101"
	ADDR_SFP3_PRESENT = "00100100"
	ADDR_SFP3_RATE_SEL = "00100011"
	ADDR_SFP3_TX_DISABLE = "00100000"
	ADDR_SFP3_TX_FAULT = "00100001"

Analyzing hierarchy for module <phy_new> in library <work> with parameters.
	ADDR_PHY0_CONF_0 = "00010000"
	ADDR_PHY0_CONF_1 = "00010001"
	ADDR_PHY0_CONF_2 = "00010010"
	ADDR_PHY0_CONF_3 = "00010011"
	ADDR_PHY0_CONF_4 = "00010100"
	ADDR_PHY1_CONF_0 = "00011000"
	ADDR_PHY1_CONF_1 = "00011001"
	ADDR_PHY1_CONF_2 = "00011010"
	ADDR_PHY1_CONF_3 = "00011011"
	ADDR_PHY1_CONF_4 = "00011100"
	ADDR_PHY2_CONF_0 = "00100000"
	ADDR_PHY2_CONF_1 = "00100001"
	ADDR_PHY2_CONF_2 = "00100010"
	ADDR_PHY2_CONF_3 = "00100011"
	ADDR_PHY2_CONF_4 = "00100100"
	ADDR_PHY3_CONF_0 = "00101000"
	ADDR_PHY3_CONF_1 = "00101001"
	ADDR_PHY3_CONF_2 = "00101010"
	ADDR_PHY3_CONF_3 = "00101011"
	ADDR_PHY3_CONF_4 = "00101100"
	ADDR_PHY_CONF_0 = "00001000"
	ADDR_PHY_CONF_1 = "00001001"
	ADDR_PHY_RESET = "00000000"

Analyzing hierarchy for module <timer> in library <work> with parameters.
	ADDR_DEVELOPER = "00100000"
	ADDR_FIRMVARE_NAME = "00011000"
	ADDR_FIRMVARE_VER = "00011001"
	ADDR_FPGA_LCELS = "00001001"
	ADDR_FPGA_SERIES = "00001000"
	ADDR_FPGA_SPEED = "00001010"
	ADDR_MICROSECOND = "00000001"
	ADDR_PRODUCER = "00010000"
	ADDR_SECOND = "00000000"
	DEVELOPER = "01000110010101010100001101001011"
	FIRMVARE_NAME = "01001101010000010100001100100000"
	FIRMVARE_VER = "00110000001100000011000000110001"
	FPGA_LCELS = "00110100001100000011000000110000"
	FPGA_SERIES = "01011000010000110011001101010011"
	FPGA_SPEED = "00110100010000110010000000100000"
	PRODUCER = "01010010010010010100111001000001"

Analyzing hierarchy for module <input_dcm> in library <work>.

Analyzing hierarchy for module <sram_write_clock> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mac_bus_mux> in library <work>.

Analyzing hierarchy for module <mac_top_new> in library <work>.

Analyzing hierarchy for module <port_regs> in library <work> with parameters.
	ADDR_ACCEPT_FRAME_TYPE = "0000001"
	ADDR_INGRESS_PRIORITY_MAP_0 = "0000011"
	ADDR_INGRESS_PRIORITY_MAP_1 = "0000100"
	ADDR_INGRESS_PRIORITY_MAP_2 = "0000101"
	ADDR_INGRESS_PRIORITY_MAP_3 = "0000110"
	ADDR_INGRESS_PRIORITY_MAP_4 = "0000111"
	ADDR_INGRESS_PRIORITY_MAP_5 = "0001000"
	ADDR_INGRESS_PRIORITY_MAP_6 = "0001001"
	ADDR_INGRESS_PRIORITY_MAP_7 = "0001010"
	ADDR_MAC_DST1_H = "1000000"
	ADDR_MAC_DST1_L = "0111111"
	ADDR_MAC_DST2_H = "1000010"
	ADDR_MAC_DST2_L = "1000001"
	ADDR_MAC_DST3_H = "1000100"
	ADDR_MAC_DST3_L = "1000011"
	ADDR_MAC_DST4_H = "1000110"
	ADDR_MAC_DST4_L = "1000101"
	ADDR_MAC_DST_ENA = "1010000"
	ADDR_MAC_DST_MASK1_H = "1001000"
	ADDR_MAC_DST_MASK1_L = "1000111"
	ADDR_MAC_DST_MASK2_H = "1001010"
	ADDR_MAC_DST_MASK2_L = "1001001"
	ADDR_MAC_DST_MASK3_H = "1001100"
	ADDR_MAC_DST_MASK3_L = "1001011"
	ADDR_MAC_DST_MASK4_H = "1001110"
	ADDR_MAC_DST_MASK4_L = "1001101"
	ADDR_MAC_DST_NUM = "1001111"
	ADDR_MAC_SRC1_H = "0100000"
	ADDR_MAC_SRC1_L = "0011111"
	ADDR_MAC_SRC2_H = "0100010"
	ADDR_MAC_SRC2_L = "0100001"
	ADDR_MAC_SRC3_H = "0100100"
	ADDR_MAC_SRC3_L = "0100011"
	ADDR_MAC_SRC4_H = "0100110"
	ADDR_MAC_SRC4_L = "0100101"
	ADDR_MAC_SRC5_H = "0101000"
	ADDR_MAC_SRC5_L = "0100111"
	ADDR_MAC_SRC6_H = "0101010"
	ADDR_MAC_SRC6_L = "0101001"
	ADDR_MAC_SRC7_H = "0101100"
	ADDR_MAC_SRC7_L = "0101011"
	ADDR_MAC_SRC8_H = "0101110"
	ADDR_MAC_SRC8_L = "0101101"
	ADDR_MAC_SRC_ENA = "0110000"
	ADDR_MAC_SRC_NUM = "0101111"
	ADDR_PORT_NUMBER = "0011001"
	ADDR_PORT_RESET = "1111111"
	ADDR_PRIORITY = "0001100"
	ADDR_STATE = "0000010"
	ADDR_TRAFFIC_CLASS_MAP_0 = "0001101"
	ADDR_TRAFFIC_CLASS_MAP_1 = "0001110"
	ADDR_TRAFFIC_CLASS_MAP_2 = "0001111"
	ADDR_TRAFFIC_CLASS_MAP_3 = "0010000"
	ADDR_TRAFFIC_CLASS_MAP_4 = "0010001"
	ADDR_TRAFFIC_CLASS_MAP_5 = "0010010"
	ADDR_TRAFFIC_CLASS_MAP_6 = "0010011"
	ADDR_TRAFFIC_CLASS_MAP_7 = "0010100"
	ADMIT_ALL = "10"
	ADMIT_TAGGED = "00"
	ADMIT_UNTAGGED = "01"
	BLOCKING = "100"
	DISABLED = "000"
	FORWARDING = "011"
	GND = "0"
	LEARNING = "010"
	LISTENING = "001"
	PORT_NUMBER = "0000"
	PORT_PRIORITY = "00000000000000000000000000000000"
	VCC = "1"

Analyzing hierarchy for module <rx_buffer_new> in library <work>.

Analyzing hierarchy for module <tx_buffer_new> in library <work>.

Analyzing hierarchy for module <port_regs> in library <work> with parameters.
	ADDR_ACCEPT_FRAME_TYPE = "0000001"
	ADDR_INGRESS_PRIORITY_MAP_0 = "0000011"
	ADDR_INGRESS_PRIORITY_MAP_1 = "0000100"
	ADDR_INGRESS_PRIORITY_MAP_2 = "0000101"
	ADDR_INGRESS_PRIORITY_MAP_3 = "0000110"
	ADDR_INGRESS_PRIORITY_MAP_4 = "0000111"
	ADDR_INGRESS_PRIORITY_MAP_5 = "0001000"
	ADDR_INGRESS_PRIORITY_MAP_6 = "0001001"
	ADDR_INGRESS_PRIORITY_MAP_7 = "0001010"
	ADDR_MAC_DST1_H = "1000000"
	ADDR_MAC_DST1_L = "0111111"
	ADDR_MAC_DST2_H = "1000010"
	ADDR_MAC_DST2_L = "1000001"
	ADDR_MAC_DST3_H = "1000100"
	ADDR_MAC_DST3_L = "1000011"
	ADDR_MAC_DST4_H = "1000110"
	ADDR_MAC_DST4_L = "1000101"
	ADDR_MAC_DST_ENA = "1010000"
	ADDR_MAC_DST_MASK1_H = "1001000"
	ADDR_MAC_DST_MASK1_L = "1000111"
	ADDR_MAC_DST_MASK2_H = "1001010"
	ADDR_MAC_DST_MASK2_L = "1001001"
	ADDR_MAC_DST_MASK3_H = "1001100"
	ADDR_MAC_DST_MASK3_L = "1001011"
	ADDR_MAC_DST_MASK4_H = "1001110"
	ADDR_MAC_DST_MASK4_L = "1001101"
	ADDR_MAC_DST_NUM = "1001111"
	ADDR_MAC_SRC1_H = "0100000"
	ADDR_MAC_SRC1_L = "0011111"
	ADDR_MAC_SRC2_H = "0100010"
	ADDR_MAC_SRC2_L = "0100001"
	ADDR_MAC_SRC3_H = "0100100"
	ADDR_MAC_SRC3_L = "0100011"
	ADDR_MAC_SRC4_H = "0100110"
	ADDR_MAC_SRC4_L = "0100101"
	ADDR_MAC_SRC5_H = "0101000"
	ADDR_MAC_SRC5_L = "0100111"
	ADDR_MAC_SRC6_H = "0101010"
	ADDR_MAC_SRC6_L = "0101001"
	ADDR_MAC_SRC7_H = "0101100"
	ADDR_MAC_SRC7_L = "0101011"
	ADDR_MAC_SRC8_H = "0101110"
	ADDR_MAC_SRC8_L = "0101101"
	ADDR_MAC_SRC_ENA = "0110000"
	ADDR_MAC_SRC_NUM = "0101111"
	ADDR_PORT_NUMBER = "0011001"
	ADDR_PORT_RESET = "1111111"
	ADDR_PRIORITY = "0001100"
	ADDR_STATE = "0000010"
	ADDR_TRAFFIC_CLASS_MAP_0 = "0001101"
	ADDR_TRAFFIC_CLASS_MAP_1 = "0001110"
	ADDR_TRAFFIC_CLASS_MAP_2 = "0001111"
	ADDR_TRAFFIC_CLASS_MAP_3 = "0010000"
	ADDR_TRAFFIC_CLASS_MAP_4 = "0010001"
	ADDR_TRAFFIC_CLASS_MAP_5 = "0010010"
	ADDR_TRAFFIC_CLASS_MAP_6 = "0010011"
	ADDR_TRAFFIC_CLASS_MAP_7 = "0010100"
	ADMIT_ALL = "10"
	ADMIT_TAGGED = "00"
	ADMIT_UNTAGGED = "01"
	BLOCKING = "100"
	DISABLED = "000"
	FORWARDING = "011"
	GND = "0"
	LEARNING = "010"
	LISTENING = "001"
	PORT_NUMBER = "0000"
	PORT_PRIORITY = "00000000000000000000000000000010"
	VCC = "1"

Analyzing hierarchy for module <port_regs> in library <work> with parameters.
	ADDR_ACCEPT_FRAME_TYPE = "0000001"
	ADDR_INGRESS_PRIORITY_MAP_0 = "0000011"
	ADDR_INGRESS_PRIORITY_MAP_1 = "0000100"
	ADDR_INGRESS_PRIORITY_MAP_2 = "0000101"
	ADDR_INGRESS_PRIORITY_MAP_3 = "0000110"
	ADDR_INGRESS_PRIORITY_MAP_4 = "0000111"
	ADDR_INGRESS_PRIORITY_MAP_5 = "0001000"
	ADDR_INGRESS_PRIORITY_MAP_6 = "0001001"
	ADDR_INGRESS_PRIORITY_MAP_7 = "0001010"
	ADDR_MAC_DST1_H = "1000000"
	ADDR_MAC_DST1_L = "0111111"
	ADDR_MAC_DST2_H = "1000010"
	ADDR_MAC_DST2_L = "1000001"
	ADDR_MAC_DST3_H = "1000100"
	ADDR_MAC_DST3_L = "1000011"
	ADDR_MAC_DST4_H = "1000110"
	ADDR_MAC_DST4_L = "1000101"
	ADDR_MAC_DST_ENA = "1010000"
	ADDR_MAC_DST_MASK1_H = "1001000"
	ADDR_MAC_DST_MASK1_L = "1000111"
	ADDR_MAC_DST_MASK2_H = "1001010"
	ADDR_MAC_DST_MASK2_L = "1001001"
	ADDR_MAC_DST_MASK3_H = "1001100"
	ADDR_MAC_DST_MASK3_L = "1001011"
	ADDR_MAC_DST_MASK4_H = "1001110"
	ADDR_MAC_DST_MASK4_L = "1001101"
	ADDR_MAC_DST_NUM = "1001111"
	ADDR_MAC_SRC1_H = "0100000"
	ADDR_MAC_SRC1_L = "0011111"
	ADDR_MAC_SRC2_H = "0100010"
	ADDR_MAC_SRC2_L = "0100001"
	ADDR_MAC_SRC3_H = "0100100"
	ADDR_MAC_SRC3_L = "0100011"
	ADDR_MAC_SRC4_H = "0100110"
	ADDR_MAC_SRC4_L = "0100101"
	ADDR_MAC_SRC5_H = "0101000"
	ADDR_MAC_SRC5_L = "0100111"
	ADDR_MAC_SRC6_H = "0101010"
	ADDR_MAC_SRC6_L = "0101001"
	ADDR_MAC_SRC7_H = "0101100"
	ADDR_MAC_SRC7_L = "0101011"
	ADDR_MAC_SRC8_H = "0101110"
	ADDR_MAC_SRC8_L = "0101101"
	ADDR_MAC_SRC_ENA = "0110000"
	ADDR_MAC_SRC_NUM = "0101111"
	ADDR_PORT_NUMBER = "0011001"
	ADDR_PORT_RESET = "1111111"
	ADDR_PRIORITY = "0001100"
	ADDR_STATE = "0000010"
	ADDR_TRAFFIC_CLASS_MAP_0 = "0001101"
	ADDR_TRAFFIC_CLASS_MAP_1 = "0001110"
	ADDR_TRAFFIC_CLASS_MAP_2 = "0001111"
	ADDR_TRAFFIC_CLASS_MAP_3 = "0010000"
	ADDR_TRAFFIC_CLASS_MAP_4 = "0010001"
	ADDR_TRAFFIC_CLASS_MAP_5 = "0010010"
	ADDR_TRAFFIC_CLASS_MAP_6 = "0010011"
	ADDR_TRAFFIC_CLASS_MAP_7 = "0010100"
	ADMIT_ALL = "10"
	ADMIT_TAGGED = "00"
	ADMIT_UNTAGGED = "01"
	BLOCKING = "100"
	DISABLED = "000"
	FORWARDING = "011"
	GND = "0"
	LEARNING = "010"
	LISTENING = "001"
	PORT_NUMBER = "0000"
	PORT_PRIORITY = "00000000000000000000000000000100"
	VCC = "1"

Analyzing hierarchy for module <port_regs> in library <work> with parameters.
	ADDR_ACCEPT_FRAME_TYPE = "0000001"
	ADDR_INGRESS_PRIORITY_MAP_0 = "0000011"
	ADDR_INGRESS_PRIORITY_MAP_1 = "0000100"
	ADDR_INGRESS_PRIORITY_MAP_2 = "0000101"
	ADDR_INGRESS_PRIORITY_MAP_3 = "0000110"
	ADDR_INGRESS_PRIORITY_MAP_4 = "0000111"
	ADDR_INGRESS_PRIORITY_MAP_5 = "0001000"
	ADDR_INGRESS_PRIORITY_MAP_6 = "0001001"
	ADDR_INGRESS_PRIORITY_MAP_7 = "0001010"
	ADDR_MAC_DST1_H = "1000000"
	ADDR_MAC_DST1_L = "0111111"
	ADDR_MAC_DST2_H = "1000010"
	ADDR_MAC_DST2_L = "1000001"
	ADDR_MAC_DST3_H = "1000100"
	ADDR_MAC_DST3_L = "1000011"
	ADDR_MAC_DST4_H = "1000110"
	ADDR_MAC_DST4_L = "1000101"
	ADDR_MAC_DST_ENA = "1010000"
	ADDR_MAC_DST_MASK1_H = "1001000"
	ADDR_MAC_DST_MASK1_L = "1000111"
	ADDR_MAC_DST_MASK2_H = "1001010"
	ADDR_MAC_DST_MASK2_L = "1001001"
	ADDR_MAC_DST_MASK3_H = "1001100"
	ADDR_MAC_DST_MASK3_L = "1001011"
	ADDR_MAC_DST_MASK4_H = "1001110"
	ADDR_MAC_DST_MASK4_L = "1001101"
	ADDR_MAC_DST_NUM = "1001111"
	ADDR_MAC_SRC1_H = "0100000"
	ADDR_MAC_SRC1_L = "0011111"
	ADDR_MAC_SRC2_H = "0100010"
	ADDR_MAC_SRC2_L = "0100001"
	ADDR_MAC_SRC3_H = "0100100"
	ADDR_MAC_SRC3_L = "0100011"
	ADDR_MAC_SRC4_H = "0100110"
	ADDR_MAC_SRC4_L = "0100101"
	ADDR_MAC_SRC5_H = "0101000"
	ADDR_MAC_SRC5_L = "0100111"
	ADDR_MAC_SRC6_H = "0101010"
	ADDR_MAC_SRC6_L = "0101001"
	ADDR_MAC_SRC7_H = "0101100"
	ADDR_MAC_SRC7_L = "0101011"
	ADDR_MAC_SRC8_H = "0101110"
	ADDR_MAC_SRC8_L = "0101101"
	ADDR_MAC_SRC_ENA = "0110000"
	ADDR_MAC_SRC_NUM = "0101111"
	ADDR_PORT_NUMBER = "0011001"
	ADDR_PORT_RESET = "1111111"
	ADDR_PRIORITY = "0001100"
	ADDR_STATE = "0000010"
	ADDR_TRAFFIC_CLASS_MAP_0 = "0001101"
	ADDR_TRAFFIC_CLASS_MAP_1 = "0001110"
	ADDR_TRAFFIC_CLASS_MAP_2 = "0001111"
	ADDR_TRAFFIC_CLASS_MAP_3 = "0010000"
	ADDR_TRAFFIC_CLASS_MAP_4 = "0010001"
	ADDR_TRAFFIC_CLASS_MAP_5 = "0010010"
	ADDR_TRAFFIC_CLASS_MAP_6 = "0010011"
	ADDR_TRAFFIC_CLASS_MAP_7 = "0010100"
	ADMIT_ALL = "10"
	ADMIT_TAGGED = "00"
	ADMIT_UNTAGGED = "01"
	BLOCKING = "100"
	DISABLED = "000"
	FORWARDING = "011"
	GND = "0"
	LEARNING = "010"
	LISTENING = "001"
	PORT_NUMBER = "0000"
	PORT_PRIORITY = "00000000000000000000000000000110"
	VCC = "1"

Analyzing hierarchy for module <rx_packet_counters> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <tx_ddr> in library <work>.

Analyzing hierarchy for module <rx_ddr> in library <work>.

Analyzing hierarchy for module <pci_to_mac_fsm> in library <work> with parameters.
	STATE_BUSY = "01"
	STATE_END = "10"
	STATE_PAUSE = "00"

Analyzing hierarchy for module <sram_write_mux> in library <work>.

Analyzing hierarchy for module <sram_read_mux> in library <work>.

Analyzing hierarchy for module <sram_read_clock> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <sram_address> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <sram_write> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <sram_read_new> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <mdio_fsm> in library <work> with parameters.
	STATE_DATA_READ = "110"
	STATE_DATA_WRITE = "111"
	STATE_IDLE = "000"
	STATE_OPCODE = "010"
	STATE_PHY_ADDR = "011"
	STATE_REG_ADDR = "100"
	STATE_START = "001"
	STATE_TA = "101"

Analyzing hierarchy for module <iic_state_machine> in library <work> with parameters.
	IIC_CLOCK_PERIOD = "001001011000"
	STATE_ACK_MASTER = "0100"
	STATE_ACK_SLAVE = "0011"
	STATE_ADDR = "0101"
	STATE_DEVSEL_RW = "0010"
	STATE_PAUSE = "0000"
	STATE_RECEIVE = "0110"
	STATE_START = "0001"
	STATE_STOP = "1000"
	STATE_TRANSMIT = "0111"

Analyzing hierarchy for module <sfp_irq> in library <work>.

Analyzing hierarchy for module <sfp_als> in library <work>.

Analyzing hierarchy for module <reset_gen> in library <work> with parameters.
	STATE_NORMAL = "1"
	STATE_RESET = "0"

Analyzing hierarchy for module <regs_int> in library <work> with parameters.
	RMON_OFFSET = "01000000"
	STATE_PAUSE = "0"
	STATE_READ = "1"

Analyzing hierarchy for module <clock_ctrl_new> in library <work> with parameters.
	TX_BUFG_ENA = "00000000000000000000000000000000"

Analyzing hierarchy for module <phy_int_new> in library <work>.

Analyzing hierarchy for module <mac_rx> in library <work>.

Analyzing hierarchy for module <mac_tx> in library <work>.

Analyzing hierarchy for module <rmon> in library <work>.

Analyzing hierarchy for module <rx_write_fsm> in library <work> with parameters.
	ADMIT_ALL = "10"
	ADMIT_TAGGED = "00"
	ADMIT_UNTAGGED = "01"
	BLOCKING = "100"
	DISABLED = "000"
	FORWARDING = "011"
	GND = "0"
	LEARNING = "010"
	LISTENING = "001"
	STATE_DATA = "0110"
	STATE_END = "1000"
	STATE_FINISH = "0111"
	STATE_HEADER = "0100"
	STATE_IN_FILTER = "0101"
	STATE_MSEC = "0010"
	STATE_PAUSE = "0011"
	STATE_PORT = "0000"
	STATE_SEC = "0001"
	VCC = "1"
	VLAN_TYPE = "1000000100000000"

Analyzing hierarchy for module <rx_read_fsm> in library <work> with parameters.
	GND = "0"
	STATE_DELAY = "001"
	STATE_END = "100"
	STATE_PAUSE = "000"
	STATE_READ1 = "010"
	STATE_READ2 = "011"
	VCC = "1"

Analyzing hierarchy for module <tx_buffer_fsm_new> in library <work> with parameters.
	WRITE_ENA_LEVEL = "00000000000000000000011001110000"

Analyzing hierarchy for module <tx_write_fsm> in library <work> with parameters.
	STATE_DATA = "01"
	STATE_END = "11"
	STATE_PAUSE = "00"

Analyzing hierarchy for module <tx_read_fsm> in library <work> with parameters.
	STATE_DATA = "101"
	STATE_END = "110"
	STATE_MSEC = "011"
	STATE_PAUSE = "000"
	STATE_PORT = "001"
	STATE_SEC = "010"
	STATE_START = "100"

Analyzing hierarchy for module <one_channel_packet_counters> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <select_source> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <tx_write> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <sram_read_dcm> in library <work>.

Analyzing hierarchy for module <one_sfp_irq> in library <work>.

Analyzing hierarchy for module <one_sfp_als> in library <work> with parameters.
	CLKDIV_RESET_BIT = "00000000000000000000000000000010"
	DELAY_BIT = "00000000000000000000000000000111"
	LOSS_BIT = "00000000000000000000000000000011"
	STABLE_BIT = "00000000000000000000000000000011"
	STATE_DELAY = "010"
	STATE_IDLE = "000"
	STATE_LOSS = "001"
	STATE_TRYLASERON = "011"
	TRYLASER_BIT = "00000000000000000000000000000101"

Analyzing hierarchy for module <short_impulse> in library <work>.

Analyzing hierarchy for module <clock_div> in library <work>.

Analyzing hierarchy for module <clock_switch> in library <work>.

Analyzing hierarchy for module <mac_rx_ctrl> in library <work> with parameters.
	Pause_idle = "0000"
	Pause_pre_syn = "0001"
	Pause_quanta_hi = "0010"
	Pause_quanta_lo = "0011"
	Pause_syn = "0100"
	State_CRCErrEnd = "1010"
	State_ErrEnd = "1001"
	State_FFFullDrop = "1011"
	State_FFFullErrEnd = "1100"
	State_IFG = "1101"
	State_OkEnd = "0111"
	State_SFD = "0010"
	State_checkCRC = "0100"
	State_data = "0011"
	State_drop = "1000"
	State_idle = "0000"
	State_preamble = "0001"

Analyzing hierarchy for module <mac_rx_ff_new> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <broadcast_filter> in library <work>.

Analyzing hierarchy for module <crc_chk> in library <work>.

Analyzing hierarchy for module <mac_rx_add_chk> in library <work>.

Analyzing hierarchy for module <mac_tx_ctrl> in library <work> with parameters.
	StateBackOff = "1001"
	StateData = "0011"
	StateDefer = "1101"
	StateFCS = "0110"
	StateFFEmptyDrop = "1011"
	StateIFG = "0111"
	StateIdle = "0000"
	StateJam = "1000"
	StateJamDrop = "1010"
	StatePAD = "0101"
	StatePause = "0100"
	StatePreamble = "0001"
	StateSFD = "0010"
	StateSendPauseFrame = "1110"
	StateSwitchNext = "1100"

Analyzing hierarchy for module <crc_gen> in library <work>.

Analyzing hierarchy for module <flow_ctrl> in library <work>.

Analyzing hierarchy for module <mac_tx_addr_add> in library <work>.

Analyzing hierarchy for module <mac_tx_ff> in library <work> with parameters.
	MAC_FFEmpty = "1010"
	MAC_FFEmpty_drop = "1011"
	MAC_FF_Err = "1101"
	MAC_byte0 = "0011"
	MAC_byte1 = "0010"
	MAC_byte2 = "0001"
	MAC_byte3 = "0000"
	MAC_idle = "1001"
	MAC_pkt_sub = "1100"
	MAC_retry = "1000"
	MAC_wait_finish = "0100"
	SYS_DROP = "0100"
	SYS_EOP_err = "0111"
	SYS_EOP_ok = "0101"
	SYS_FFEmpty = "0110"
	SYS_MOP = "0011"
	SYS_SOP = "0010"
	SYS_SOP_err = "1000"
	SYS_WaitSop = "0001"
	SYS_idle = "0000"

Analyzing hierarchy for module <ramdon_gen> in library <work>.

Analyzing hierarchy for module <rmon_addr_gen> in library <work> with parameters.
	StateIdle = "0000"
	StatePktLength = "0001"
	StatePktNumber = "0010"
	StatePktRange = "0100"
	StatePktType = "0011"

Analyzing hierarchy for module <rmon_ctrl> in library <work> with parameters.
	StateCPU = "0000"
	StateMAC0 = "0001"
	StateMAC1 = "0010"

Analyzing hierarchy for module <rmon_dpram> in library <work>.

Analyzing hierarchy for module <mux_priority> in library <work>.

Analyzing hierarchy for module <sram_addr_count> in library <work> with parameters.
	STATE_INC = "01"
	STATE_LOAD = "10"
	STATE_PAUSE = "00"

Analyzing hierarchy for module <priority_packet_counter> in library <work> with parameters.
	GND = "0"
	VCC = "1"

Analyzing hierarchy for module <priority_rd_addr_counter> in library <work>.

Analyzing hierarchy for module <mac_rx_ff_write> in library <work> with parameters.
	MAC_RX_FF_DEPTH = "00000000000000000000000000001001"
	State_be0 = "0100"
	State_be1 = "0111"
	State_be2 = "0110"
	State_be3 = "0101"
	State_byte0 = "0011"
	State_byte1 = "0010"
	State_byte2 = "0001"
	State_byte3 = "0000"
	State_err_end = "1000"
	State_idle = "1001"

Analyzing hierarchy for module <mac_rx_ff_read> in library <work> with parameters.
	FF_emtpy_err = "100"
	MAC_RX_FF_DEPTH = "00000000000000000000000000001001"
	SYS_idle = "011"
	SYS_pause = "001"
	SYS_read = "000"
	SYS_wait_end = "010"

Analyzing hierarchy for module <M8_1E> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <top>.
	GND = 1'b0
	VCC = 1'b1
	Calling function <MuxIicSdaIn>.
Module <top> is correct for synthesis.
 
Analyzing module <clock_gen> in library <work>.
	GND = 1'b0
	PERIOD_OF_MHZ = 7'b1111100
	VCC = 1'b1
Module <clock_gen> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <rx_clockx1> in unit <clock_gen>.
    Set user-defined property "DIFF_TERM =  FALSE" for instance <rx_clockx1> in unit <clock_gen>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <rx_clockx1> in unit <clock_gen>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <rx_clockx1> in unit <clock_gen>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <rx_clockx1> in unit <clock_gen>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <rx_clockx1> in unit <clock_gen>.
Analyzing module <input_dcm> in library <work>.
Module <input_dcm> is correct for synthesis.
 
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLKIN_PERIOD =  8.000000" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  FIXED" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "PHASE_SHIFT =  64" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "SIM_MODE =  SAFE" for instance <DCM_INST> in unit <input_dcm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <input_dcm>.
Analyzing module <sram_write_clock> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_write_clock> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <fddr_clock> in unit <sram_write_clock>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf> in unit <sram_write_clock>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf> in unit <sram_write_clock>.
Analyzing module <spi_to_epc> in library <work>.
	GND = 1'b0
	STATE_DATA_RECEIVE = 3'b011
	STATE_DATA_TRANSMIT = 3'b100
	STATE_PAUSE = 3'b000
	STATE_REG_ADDR = 3'b010
	STATE_SLAVE_ADDR = 3'b001
	VCC = 1'b1
	Calling function <Decoder>.
	Calling function <Mux>.
Module <spi_to_epc> is correct for synthesis.
 
Analyzing module <mac_and_buf.1> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <mac_and_buf.1> is correct for synthesis.
 
Analyzing module <mac_bus_mux> in library <work>.
Module <mac_bus_mux> is correct for synthesis.
 
Analyzing module <mac_top_new> in library <work>.
Module <mac_top_new> is correct for synthesis.
 
Analyzing module <regs_int> in library <work>.
	RMON_OFFSET = 8'b01000000
	STATE_PAUSE = 1'b0
	STATE_READ = 1'b1
	Calling function <MuxData>.
Module <regs_int> is correct for synthesis.
 
Analyzing module <short_impulse> in library <work>.
Module <short_impulse> is correct for synthesis.
 
Analyzing module <clock_ctrl_new> in library <work>.
	TX_BUFG_ENA = 32'sb00000000000000000000000000000000
Module <clock_ctrl_new> is correct for synthesis.
 
Analyzing module <clock_div> in library <work>.
Module <clock_div> is correct for synthesis.
 
Analyzing module <clock_switch> in library <work>.
Module <clock_switch> is correct for synthesis.
 
Analyzing module <phy_int_new> in library <work>.
Module <phy_int_new> is correct for synthesis.
 
Analyzing module <mac_rx> in library <work>.
Module <mac_rx> is correct for synthesis.
 
Analyzing module <mac_rx_ctrl> in library <work>.
	Pause_idle = 4'b0000
	Pause_pre_syn = 4'b0001
	Pause_quanta_hi = 4'b0010
	Pause_quanta_lo = 4'b0011
	Pause_syn = 4'b0100
	State_CRCErrEnd = 4'b1010
	State_ErrEnd = 4'b1001
	State_FFFullDrop = 4'b1011
	State_FFFullErrEnd = 4'b1100
	State_IFG = 4'b1101
	State_OkEnd = 4'b0111
	State_SFD = 4'b0010
	State_checkCRC = 4'b0100
	State_data = 4'b0011
	State_drop = 4'b1000
	State_idle = 4'b0000
	State_preamble = 4'b0001
Module <mac_rx_ctrl> is correct for synthesis.
 
Analyzing module <mac_rx_ff_new> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <mac_rx_ff_new> is correct for synthesis.
 
Analyzing module <mac_rx_ff_write> in library <work>.
	MAC_RX_FF_DEPTH = 32'sb00000000000000000000000000001001
	State_be0 = 4'b0100
	State_be1 = 4'b0111
	State_be2 = 4'b0110
	State_be3 = 4'b0101
	State_byte0 = 4'b0011
	State_byte1 = 4'b0010
	State_byte2 = 4'b0001
	State_byte3 = 4'b0000
	State_err_end = 4'b1000
	State_idle = 4'b1001
Module <mac_rx_ff_write> is correct for synthesis.
 
Analyzing module <mac_rx_ff_read> in library <work>.
	FF_emtpy_err = 3'b100
	MAC_RX_FF_DEPTH = 32'sb00000000000000000000000000001001
	SYS_idle = 3'b011
	SYS_pause = 3'b001
	SYS_read = 3'b000
	SYS_wait_end = 3'b010
Module <mac_rx_ff_read> is correct for synthesis.
 
Analyzing module <broadcast_filter> in library <work>.
Module <broadcast_filter> is correct for synthesis.
 
Analyzing module <crc_chk> in library <work>.
	Calling function <NextCRC>.
Module <crc_chk> is correct for synthesis.
 
Analyzing module <mac_rx_add_chk> in library <work>.
Module <mac_rx_add_chk> is correct for synthesis.
 
Analyzing module <mac_tx> in library <work>.
Module <mac_tx> is correct for synthesis.
 
Analyzing module <mac_tx_ctrl> in library <work>.
	StateBackOff = 4'b1001
	StateData = 4'b0011
	StateDefer = 4'b1101
	StateFCS = 4'b0110
	StateFFEmptyDrop = 4'b1011
	StateIFG = 4'b0111
	StateIdle = 4'b0000
	StateJam = 4'b1000
	StateJamDrop = 4'b1010
	StatePAD = 4'b0101
	StatePause = 4'b0100
	StatePreamble = 4'b0001
	StateSFD = 4'b0010
	StateSendPauseFrame = 4'b1110
	StateSwitchNext = 4'b1100
Module <mac_tx_ctrl> is correct for synthesis.
 
    Set property "syn_keep = 1" for signal <Current_state>.
Analyzing module <crc_gen> in library <work>.
	Calling function <NextCRC>.
Module <crc_gen> is correct for synthesis.
 
Analyzing module <flow_ctrl> in library <work>.
Module <flow_ctrl> is correct for synthesis.
 
Analyzing module <mac_tx_addr_add> in library <work>.
WARNING:Xst:916 - "src/mac_src/mac_tx/mac_tx_addr_add.v" line 44: Delay is ignored for synthesis.
WARNING:Xst:916 - "src/mac_src/mac_tx/mac_tx_addr_add.v" line 45: Delay is ignored for synthesis.
WARNING:Xst:916 - "src/mac_src/mac_tx/mac_tx_addr_add.v" line 46: Delay is ignored for synthesis.
Module <mac_tx_addr_add> is correct for synthesis.
 
Analyzing module <mac_tx_ff> in library <work>.
	MAC_FFEmpty = 4'b1010
	MAC_FFEmpty_drop = 4'b1011
	MAC_FF_Err = 4'b1101
	MAC_byte0 = 4'b0011
	MAC_byte1 = 4'b0010
	MAC_byte2 = 4'b0001
	MAC_byte3 = 4'b0000
	MAC_idle = 4'b1001
	MAC_pkt_sub = 4'b1100
	MAC_retry = 4'b1000
	MAC_wait_finish = 4'b0100
	SYS_DROP = 4'b0100
	SYS_EOP_err = 4'b0111
	SYS_EOP_ok = 4'b0101
	SYS_FFEmpty = 4'b0110
	SYS_MOP = 4'b0011
	SYS_SOP = 4'b0010
	SYS_SOP_err = 4'b1000
	SYS_WaitSop = 4'b0001
	SYS_idle = 4'b0000
WARNING:Xst:905 - "src/mac_src/mac_tx/mac_tx_ff.v" line 684: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <Dout_BE>
Module <mac_tx_ff> is correct for synthesis.
 
    Set property "syn_preserve = 1" for signal <Packet_number_add>.
    Set property "syn_keep = 1" for signal <Dout_reg_en>.
    Set property "syn_keep = 1" for signal <Empty>.
    Set property "syn_preserve = 1" for signal <Current_state_MAC_reg>.
    Set property "syn_preserve = 1" for signal <Current_state_SYS>.
    Set property "syn_preserve = 1" for signal <Packet_number_inFF_reg>.
    Set property "syn_preserve = 1" for signal <Packet_number_sub_edge>.
    Set property "syn_keep = 1" for signal <AlmostFull>.
    Set property "syn_keep = 1" for signal <Add_rd_add>.
    Set property "syn_preserve = 1" for signal <Dout_reg>.
    Set property "syn_keep = 1" for signal <Full>.
    Set property "syn_keep = 1" for signal <Packet_number_inFF>.
    Set property "syn_preserve = 1" for signal <Current_state_MAC>.
Analyzing module <ramdon_gen> in library <work>.
Module <ramdon_gen> is correct for synthesis.
 
Analyzing module <rmon> in library <work>.
Module <rmon> is correct for synthesis.
 
Analyzing module <rmon_addr_gen> in library <work>.
	StateIdle = 4'b0000
	StatePktLength = 4'b0001
	StatePktNumber = 4'b0010
	StatePktRange = 4'b0100
	StatePktType = 4'b0011
Module <rmon_addr_gen> is correct for synthesis.
 
Analyzing module <rmon_ctrl> in library <work>.
	StateCPU = 4'b0000
	StateMAC0 = 4'b0001
	StateMAC1 = 4'b0010
Module <rmon_ctrl> is correct for synthesis.
 
Analyzing module <rmon_dpram> in library <work>.
Module <rmon_dpram> is correct for synthesis.
 
Analyzing module <port_regs.1> in library <work>.
	ADDR_ACCEPT_FRAME_TYPE = 7'b0000001
	ADDR_INGRESS_PRIORITY_MAP_0 = 7'b0000011
	ADDR_INGRESS_PRIORITY_MAP_1 = 7'b0000100
	ADDR_INGRESS_PRIORITY_MAP_2 = 7'b0000101
	ADDR_INGRESS_PRIORITY_MAP_3 = 7'b0000110
	ADDR_INGRESS_PRIORITY_MAP_4 = 7'b0000111
	ADDR_INGRESS_PRIORITY_MAP_5 = 7'b0001000
	ADDR_INGRESS_PRIORITY_MAP_6 = 7'b0001001
	ADDR_INGRESS_PRIORITY_MAP_7 = 7'b0001010
	ADDR_MAC_DST1_H = 7'b1000000
	ADDR_MAC_DST1_L = 7'b0111111
	ADDR_MAC_DST2_H = 7'b1000010
	ADDR_MAC_DST2_L = 7'b1000001
	ADDR_MAC_DST3_H = 7'b1000100
	ADDR_MAC_DST3_L = 7'b1000011
	ADDR_MAC_DST4_H = 7'b1000110
	ADDR_MAC_DST4_L = 7'b1000101
	ADDR_MAC_DST_ENA = 7'b1010000
	ADDR_MAC_DST_MASK1_H = 7'b1001000
	ADDR_MAC_DST_MASK1_L = 7'b1000111
	ADDR_MAC_DST_MASK2_H = 7'b1001010
	ADDR_MAC_DST_MASK2_L = 7'b1001001
	ADDR_MAC_DST_MASK3_H = 7'b1001100
	ADDR_MAC_DST_MASK3_L = 7'b1001011
	ADDR_MAC_DST_MASK4_H = 7'b1001110
	ADDR_MAC_DST_MASK4_L = 7'b1001101
	ADDR_MAC_DST_NUM = 7'b1001111
	ADDR_MAC_SRC1_H = 7'b0100000
	ADDR_MAC_SRC1_L = 7'b0011111
	ADDR_MAC_SRC2_H = 7'b0100010
	ADDR_MAC_SRC2_L = 7'b0100001
	ADDR_MAC_SRC3_H = 7'b0100100
	ADDR_MAC_SRC3_L = 7'b0100011
	ADDR_MAC_SRC4_H = 7'b0100110
	ADDR_MAC_SRC4_L = 7'b0100101
	ADDR_MAC_SRC5_H = 7'b0101000
	ADDR_MAC_SRC5_L = 7'b0100111
	ADDR_MAC_SRC6_H = 7'b0101010
	ADDR_MAC_SRC6_L = 7'b0101001
	ADDR_MAC_SRC7_H = 7'b0101100
	ADDR_MAC_SRC7_L = 7'b0101011
	ADDR_MAC_SRC8_H = 7'b0101110
	ADDR_MAC_SRC8_L = 7'b0101101
	ADDR_MAC_SRC_ENA = 7'b0110000
	ADDR_MAC_SRC_NUM = 7'b0101111
	ADDR_PORT_NUMBER = 7'b0011001
	ADDR_PORT_RESET = 7'b1111111
	ADDR_PRIORITY = 7'b0001100
	ADDR_STATE = 7'b0000010
	ADDR_TRAFFIC_CLASS_MAP_0 = 7'b0001101
	ADDR_TRAFFIC_CLASS_MAP_1 = 7'b0001110
	ADDR_TRAFFIC_CLASS_MAP_2 = 7'b0001111
	ADDR_TRAFFIC_CLASS_MAP_3 = 7'b0010000
	ADDR_TRAFFIC_CLASS_MAP_4 = 7'b0010001
	ADDR_TRAFFIC_CLASS_MAP_5 = 7'b0010010
	ADDR_TRAFFIC_CLASS_MAP_6 = 7'b0010011
	ADDR_TRAFFIC_CLASS_MAP_7 = 7'b0010100
	ADMIT_ALL = 2'b10
	ADMIT_TAGGED = 2'b00
	ADMIT_UNTAGGED = 2'b01
	BLOCKING = 3'b100
	DISABLED = 3'b000
	FORWARDING = 3'b011
	GND = 1'b0
	LEARNING = 3'b010
	LISTENING = 3'b001
	PORT_NUMBER = 4'b0000
	PORT_PRIORITY = 32'sb00000000000000000000000000000000
	VCC = 1'b1
	Calling function <MacMux>.
	Calling function <MacMux>.
	Calling function <MacMux>.
Module <port_regs.1> is correct for synthesis.
 
Analyzing module <rx_buffer_new> in library <work>.
Module <rx_buffer_new> is correct for synthesis.
 
Analyzing module <rx_write_fsm> in library <work>.
	ADMIT_ALL = 2'b10
	ADMIT_TAGGED = 2'b00
	ADMIT_UNTAGGED = 2'b01
	BLOCKING = 3'b100
	DISABLED = 3'b000
	FORWARDING = 3'b011
	GND = 1'b0
	LEARNING = 3'b010
	LISTENING = 3'b001
	STATE_DATA = 4'b0110
	STATE_END = 4'b1000
	STATE_FINISH = 4'b0111
	STATE_HEADER = 4'b0100
	STATE_IN_FILTER = 4'b0101
	STATE_MSEC = 4'b0010
	STATE_PAUSE = 4'b0011
	STATE_PORT = 4'b0000
	STATE_SEC = 4'b0001
	VCC = 1'b1
	VLAN_TYPE = 16'b1000000100000000
Module <rx_write_fsm> is correct for synthesis.
 
Analyzing module <mux_priority> in library <work>.
Module <mux_priority> is correct for synthesis.
 
Analyzing module <M8_1E> in library <work>.
Module <M8_1E> is correct for synthesis.
 
Analyzing module <rx_read_fsm> in library <work>.
	GND = 1'b0
	STATE_DELAY = 3'b001
	STATE_END = 3'b100
	STATE_PAUSE = 3'b000
	STATE_READ1 = 3'b010
	STATE_READ2 = 3'b011
	VCC = 1'b1
	Calling function <MuxSramWriteAddr>.
Module <rx_read_fsm> is correct for synthesis.
 
Analyzing module <sram_addr_count> in library <work>.
	STATE_INC = 2'b01
	STATE_LOAD = 2'b10
	STATE_PAUSE = 2'b00
Module <sram_addr_count> is correct for synthesis.
 
Analyzing module <tx_buffer_new> in library <work>.
Module <tx_buffer_new> is correct for synthesis.
 
Analyzing module <tx_buffer_fsm_new> in library <work>.
	WRITE_ENA_LEVEL = 32'sb00000000000000000000011001110000
Module <tx_buffer_fsm_new> is correct for synthesis.
 
Analyzing module <tx_write_fsm> in library <work>.
	STATE_DATA = 2'b01
	STATE_END = 2'b11
	STATE_PAUSE = 2'b00
Module <tx_write_fsm> is correct for synthesis.
 
Analyzing module <tx_read_fsm> in library <work>.
	STATE_DATA = 3'b101
	STATE_END = 3'b110
	STATE_MSEC = 3'b011
	STATE_PAUSE = 3'b000
	STATE_PORT = 3'b001
	STATE_SEC = 3'b010
	STATE_START = 3'b100
Module <tx_read_fsm> is correct for synthesis.
 
Analyzing module <mac_and_buf.2> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <mac_and_buf.2> is correct for synthesis.
 
Analyzing module <port_regs.2> in library <work>.
	ADDR_ACCEPT_FRAME_TYPE = 7'b0000001
	ADDR_INGRESS_PRIORITY_MAP_0 = 7'b0000011
	ADDR_INGRESS_PRIORITY_MAP_1 = 7'b0000100
	ADDR_INGRESS_PRIORITY_MAP_2 = 7'b0000101
	ADDR_INGRESS_PRIORITY_MAP_3 = 7'b0000110
	ADDR_INGRESS_PRIORITY_MAP_4 = 7'b0000111
	ADDR_INGRESS_PRIORITY_MAP_5 = 7'b0001000
	ADDR_INGRESS_PRIORITY_MAP_6 = 7'b0001001
	ADDR_INGRESS_PRIORITY_MAP_7 = 7'b0001010
	ADDR_MAC_DST1_H = 7'b1000000
	ADDR_MAC_DST1_L = 7'b0111111
	ADDR_MAC_DST2_H = 7'b1000010
	ADDR_MAC_DST2_L = 7'b1000001
	ADDR_MAC_DST3_H = 7'b1000100
	ADDR_MAC_DST3_L = 7'b1000011
	ADDR_MAC_DST4_H = 7'b1000110
	ADDR_MAC_DST4_L = 7'b1000101
	ADDR_MAC_DST_ENA = 7'b1010000
	ADDR_MAC_DST_MASK1_H = 7'b1001000
	ADDR_MAC_DST_MASK1_L = 7'b1000111
	ADDR_MAC_DST_MASK2_H = 7'b1001010
	ADDR_MAC_DST_MASK2_L = 7'b1001001
	ADDR_MAC_DST_MASK3_H = 7'b1001100
	ADDR_MAC_DST_MASK3_L = 7'b1001011
	ADDR_MAC_DST_MASK4_H = 7'b1001110
	ADDR_MAC_DST_MASK4_L = 7'b1001101
	ADDR_MAC_DST_NUM = 7'b1001111
	ADDR_MAC_SRC1_H = 7'b0100000
	ADDR_MAC_SRC1_L = 7'b0011111
	ADDR_MAC_SRC2_H = 7'b0100010
	ADDR_MAC_SRC2_L = 7'b0100001
	ADDR_MAC_SRC3_H = 7'b0100100
	ADDR_MAC_SRC3_L = 7'b0100011
	ADDR_MAC_SRC4_H = 7'b0100110
	ADDR_MAC_SRC4_L = 7'b0100101
	ADDR_MAC_SRC5_H = 7'b0101000
	ADDR_MAC_SRC5_L = 7'b0100111
	ADDR_MAC_SRC6_H = 7'b0101010
	ADDR_MAC_SRC6_L = 7'b0101001
	ADDR_MAC_SRC7_H = 7'b0101100
	ADDR_MAC_SRC7_L = 7'b0101011
	ADDR_MAC_SRC8_H = 7'b0101110
	ADDR_MAC_SRC8_L = 7'b0101101
	ADDR_MAC_SRC_ENA = 7'b0110000
	ADDR_MAC_SRC_NUM = 7'b0101111
	ADDR_PORT_NUMBER = 7'b0011001
	ADDR_PORT_RESET = 7'b1111111
	ADDR_PRIORITY = 7'b0001100
	ADDR_STATE = 7'b0000010
	ADDR_TRAFFIC_CLASS_MAP_0 = 7'b0001101
	ADDR_TRAFFIC_CLASS_MAP_1 = 7'b0001110
	ADDR_TRAFFIC_CLASS_MAP_2 = 7'b0001111
	ADDR_TRAFFIC_CLASS_MAP_3 = 7'b0010000
	ADDR_TRAFFIC_CLASS_MAP_4 = 7'b0010001
	ADDR_TRAFFIC_CLASS_MAP_5 = 7'b0010010
	ADDR_TRAFFIC_CLASS_MAP_6 = 7'b0010011
	ADDR_TRAFFIC_CLASS_MAP_7 = 7'b0010100
	ADMIT_ALL = 2'b10
	ADMIT_TAGGED = 2'b00
	ADMIT_UNTAGGED = 2'b01
	BLOCKING = 3'b100
	DISABLED = 3'b000
	FORWARDING = 3'b011
	GND = 1'b0
	LEARNING = 3'b010
	LISTENING = 3'b001
	PORT_NUMBER = 4'b0000
	PORT_PRIORITY = 32'sb00000000000000000000000000000010
	VCC = 1'b1
	Calling function <MacMux>.
	Calling function <MacMux>.
	Calling function <MacMux>.
Module <port_regs.2> is correct for synthesis.
 
Analyzing module <mac_and_buf.3> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <mac_and_buf.3> is correct for synthesis.
 
Analyzing module <port_regs.3> in library <work>.
	ADDR_ACCEPT_FRAME_TYPE = 7'b0000001
	ADDR_INGRESS_PRIORITY_MAP_0 = 7'b0000011
	ADDR_INGRESS_PRIORITY_MAP_1 = 7'b0000100
	ADDR_INGRESS_PRIORITY_MAP_2 = 7'b0000101
	ADDR_INGRESS_PRIORITY_MAP_3 = 7'b0000110
	ADDR_INGRESS_PRIORITY_MAP_4 = 7'b0000111
	ADDR_INGRESS_PRIORITY_MAP_5 = 7'b0001000
	ADDR_INGRESS_PRIORITY_MAP_6 = 7'b0001001
	ADDR_INGRESS_PRIORITY_MAP_7 = 7'b0001010
	ADDR_MAC_DST1_H = 7'b1000000
	ADDR_MAC_DST1_L = 7'b0111111
	ADDR_MAC_DST2_H = 7'b1000010
	ADDR_MAC_DST2_L = 7'b1000001
	ADDR_MAC_DST3_H = 7'b1000100
	ADDR_MAC_DST3_L = 7'b1000011
	ADDR_MAC_DST4_H = 7'b1000110
	ADDR_MAC_DST4_L = 7'b1000101
	ADDR_MAC_DST_ENA = 7'b1010000
	ADDR_MAC_DST_MASK1_H = 7'b1001000
	ADDR_MAC_DST_MASK1_L = 7'b1000111
	ADDR_MAC_DST_MASK2_H = 7'b1001010
	ADDR_MAC_DST_MASK2_L = 7'b1001001
	ADDR_MAC_DST_MASK3_H = 7'b1001100
	ADDR_MAC_DST_MASK3_L = 7'b1001011
	ADDR_MAC_DST_MASK4_H = 7'b1001110
	ADDR_MAC_DST_MASK4_L = 7'b1001101
	ADDR_MAC_DST_NUM = 7'b1001111
	ADDR_MAC_SRC1_H = 7'b0100000
	ADDR_MAC_SRC1_L = 7'b0011111
	ADDR_MAC_SRC2_H = 7'b0100010
	ADDR_MAC_SRC2_L = 7'b0100001
	ADDR_MAC_SRC3_H = 7'b0100100
	ADDR_MAC_SRC3_L = 7'b0100011
	ADDR_MAC_SRC4_H = 7'b0100110
	ADDR_MAC_SRC4_L = 7'b0100101
	ADDR_MAC_SRC5_H = 7'b0101000
	ADDR_MAC_SRC5_L = 7'b0100111
	ADDR_MAC_SRC6_H = 7'b0101010
	ADDR_MAC_SRC6_L = 7'b0101001
	ADDR_MAC_SRC7_H = 7'b0101100
	ADDR_MAC_SRC7_L = 7'b0101011
	ADDR_MAC_SRC8_H = 7'b0101110
	ADDR_MAC_SRC8_L = 7'b0101101
	ADDR_MAC_SRC_ENA = 7'b0110000
	ADDR_MAC_SRC_NUM = 7'b0101111
	ADDR_PORT_NUMBER = 7'b0011001
	ADDR_PORT_RESET = 7'b1111111
	ADDR_PRIORITY = 7'b0001100
	ADDR_STATE = 7'b0000010
	ADDR_TRAFFIC_CLASS_MAP_0 = 7'b0001101
	ADDR_TRAFFIC_CLASS_MAP_1 = 7'b0001110
	ADDR_TRAFFIC_CLASS_MAP_2 = 7'b0001111
	ADDR_TRAFFIC_CLASS_MAP_3 = 7'b0010000
	ADDR_TRAFFIC_CLASS_MAP_4 = 7'b0010001
	ADDR_TRAFFIC_CLASS_MAP_5 = 7'b0010010
	ADDR_TRAFFIC_CLASS_MAP_6 = 7'b0010011
	ADDR_TRAFFIC_CLASS_MAP_7 = 7'b0010100
	ADMIT_ALL = 2'b10
	ADMIT_TAGGED = 2'b00
	ADMIT_UNTAGGED = 2'b01
	BLOCKING = 3'b100
	DISABLED = 3'b000
	FORWARDING = 3'b011
	GND = 1'b0
	LEARNING = 3'b010
	LISTENING = 3'b001
	PORT_NUMBER = 4'b0000
	PORT_PRIORITY = 32'sb00000000000000000000000000000100
	VCC = 1'b1
	Calling function <MacMux>.
	Calling function <MacMux>.
	Calling function <MacMux>.
Module <port_regs.3> is correct for synthesis.
 
Analyzing module <mac_and_buf.4> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <mac_and_buf.4> is correct for synthesis.
 
Analyzing module <port_regs.4> in library <work>.
	ADDR_ACCEPT_FRAME_TYPE = 7'b0000001
	ADDR_INGRESS_PRIORITY_MAP_0 = 7'b0000011
	ADDR_INGRESS_PRIORITY_MAP_1 = 7'b0000100
	ADDR_INGRESS_PRIORITY_MAP_2 = 7'b0000101
	ADDR_INGRESS_PRIORITY_MAP_3 = 7'b0000110
	ADDR_INGRESS_PRIORITY_MAP_4 = 7'b0000111
	ADDR_INGRESS_PRIORITY_MAP_5 = 7'b0001000
	ADDR_INGRESS_PRIORITY_MAP_6 = 7'b0001001
	ADDR_INGRESS_PRIORITY_MAP_7 = 7'b0001010
	ADDR_MAC_DST1_H = 7'b1000000
	ADDR_MAC_DST1_L = 7'b0111111
	ADDR_MAC_DST2_H = 7'b1000010
	ADDR_MAC_DST2_L = 7'b1000001
	ADDR_MAC_DST3_H = 7'b1000100
	ADDR_MAC_DST3_L = 7'b1000011
	ADDR_MAC_DST4_H = 7'b1000110
	ADDR_MAC_DST4_L = 7'b1000101
	ADDR_MAC_DST_ENA = 7'b1010000
	ADDR_MAC_DST_MASK1_H = 7'b1001000
	ADDR_MAC_DST_MASK1_L = 7'b1000111
	ADDR_MAC_DST_MASK2_H = 7'b1001010
	ADDR_MAC_DST_MASK2_L = 7'b1001001
	ADDR_MAC_DST_MASK3_H = 7'b1001100
	ADDR_MAC_DST_MASK3_L = 7'b1001011
	ADDR_MAC_DST_MASK4_H = 7'b1001110
	ADDR_MAC_DST_MASK4_L = 7'b1001101
	ADDR_MAC_DST_NUM = 7'b1001111
	ADDR_MAC_SRC1_H = 7'b0100000
	ADDR_MAC_SRC1_L = 7'b0011111
	ADDR_MAC_SRC2_H = 7'b0100010
	ADDR_MAC_SRC2_L = 7'b0100001
	ADDR_MAC_SRC3_H = 7'b0100100
	ADDR_MAC_SRC3_L = 7'b0100011
	ADDR_MAC_SRC4_H = 7'b0100110
	ADDR_MAC_SRC4_L = 7'b0100101
	ADDR_MAC_SRC5_H = 7'b0101000
	ADDR_MAC_SRC5_L = 7'b0100111
	ADDR_MAC_SRC6_H = 7'b0101010
	ADDR_MAC_SRC6_L = 7'b0101001
	ADDR_MAC_SRC7_H = 7'b0101100
	ADDR_MAC_SRC7_L = 7'b0101011
	ADDR_MAC_SRC8_H = 7'b0101110
	ADDR_MAC_SRC8_L = 7'b0101101
	ADDR_MAC_SRC_ENA = 7'b0110000
	ADDR_MAC_SRC_NUM = 7'b0101111
	ADDR_PORT_NUMBER = 7'b0011001
	ADDR_PORT_RESET = 7'b1111111
	ADDR_PRIORITY = 7'b0001100
	ADDR_STATE = 7'b0000010
	ADDR_TRAFFIC_CLASS_MAP_0 = 7'b0001101
	ADDR_TRAFFIC_CLASS_MAP_1 = 7'b0001110
	ADDR_TRAFFIC_CLASS_MAP_2 = 7'b0001111
	ADDR_TRAFFIC_CLASS_MAP_3 = 7'b0010000
	ADDR_TRAFFIC_CLASS_MAP_4 = 7'b0010001
	ADDR_TRAFFIC_CLASS_MAP_5 = 7'b0010010
	ADDR_TRAFFIC_CLASS_MAP_6 = 7'b0010011
	ADDR_TRAFFIC_CLASS_MAP_7 = 7'b0010100
	ADMIT_ALL = 2'b10
	ADMIT_TAGGED = 2'b00
	ADMIT_UNTAGGED = 2'b01
	BLOCKING = 3'b100
	DISABLED = 3'b000
	FORWARDING = 3'b011
	GND = 1'b0
	LEARNING = 3'b010
	LISTENING = 3'b001
	PORT_NUMBER = 4'b0000
	PORT_PRIORITY = 32'sb00000000000000000000000000000110
	VCC = 1'b1
	Calling function <MacMux>.
	Calling function <MacMux>.
	Calling function <MacMux>.
Module <port_regs.4> is correct for synthesis.
 
Analyzing module <bus> in library <work>.
	GND = 1'b0
	STATE_CHECK = 2'b00
	STATE_NEXT = 2'b11
	STATE_READ = 2'b01
	STATE_READ_PAUSE = 1'b0
	STATE_READ_READ = 1'b1
	STATE_WRITE = 2'b10
	STATE_WRITE_END = 2'b10
	STATE_WRITE_FINISH = 2'b11
	STATE_WRITE_PAUSE = 2'b00
	STATE_WRITE_WRITE = 2'b01
	VCC = 1'b1
Module <bus> is correct for synthesis.
 
Analyzing module <rx_packet_counters> in library <work>.
	GND = 1'b0
	VCC = 1'b1
	Calling function <MuxAddr>.
	Calling function <MuxAddr>.
	Calling function <MuxAddr>.
Module <rx_packet_counters> is correct for synthesis.
 
Analyzing module <one_channel_packet_counters> in library <work>.
	GND = 1'b0
	VCC = 1'b1
	Calling function <CalcPriorityAndFull>.
	Calling function <MuxAddr>.
Module <one_channel_packet_counters> is correct for synthesis.
 
Analyzing module <priority_packet_counter> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <priority_packet_counter> is correct for synthesis.
 
Analyzing module <priority_rd_addr_counter> in library <work>.
Module <priority_rd_addr_counter> is correct for synthesis.
 
Analyzing module <select_source> in library <work>.
	GND = 1'b0
	VCC = 1'b1
	Calling function <MuxChannel>.
	Calling function <MuxChannel>.
	Calling function <MuxChannel>.
	Calling function <MuxChannel>.
	Calling function <PriorityEncoder>.
	Calling function <MuxChannelNumber>.
	Calling function <MuxPriority>.
Module <select_source> is correct for synthesis.
 
Analyzing module <serdes> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <serdes> is correct for synthesis.
 
Analyzing module <tx_ddr> in library <work>.
Module <tx_ddr> is correct for synthesis.
 
Analyzing module <tx_write> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <tx_write> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <FDC_ENVOI> in unit <tx_write>.
    Set user-defined property "INIT =  0" for instance <WRT_FDC_D1> in unit <tx_write>.
    Set user-defined property "INIT =  0" for instance <WRT_FDDR_DQ> in unit <tx_write>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <WRT_FDDR_DOBUFT> in unit <tx_write>.
    Set user-defined property "DRIVE =  12" for instance <WRT_FDDR_DOBUFT> in unit <tx_write>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <WRT_FDDR_DOBUFT> in unit <tx_write>.
    Set user-defined property "SLEW =  SLOW" for instance <WRT_FDDR_DOBUFT> in unit <tx_write>.
Analyzing module <rx_ddr> in library <work>.
Module <rx_ddr> is correct for synthesis.
 
Analyzing module <mac_mux> in library <work>.
	Calling function <MuxBit>.
Module <mac_mux> is correct for synthesis.
 
Analyzing module <pci_to_mac_fsm> in library <work>.
	STATE_BUSY = 2'b01
	STATE_END = 2'b10
	STATE_PAUSE = 2'b00
Module <pci_to_mac_fsm> is correct for synthesis.
 
Analyzing module <memory_arbiter> in library <work>.
Module <memory_arbiter> is correct for synthesis.
 
Analyzing module <sram_write_mux> in library <work>.
	Calling function <MuxEna>.
	Calling function <MuxAddr>.
	Calling function <MuxData>.
Module <sram_write_mux> is correct for synthesis.
 
Analyzing module <sram_read_mux> in library <work>.
	Calling function <MuxEna>.
	Calling function <MuxAddr>.
Module <sram_read_mux> is correct for synthesis.
 
Analyzing module <sram_ctrl> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_ctrl> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <INST_R_FD> in unit <sram_ctrl>.
    Set user-defined property "INIT =  0" for instance <INST_W_FD> in unit <sram_ctrl>.
    Set user-defined property "INIT =  0" for instance <INST_BW_FD0> in unit <sram_ctrl>.
    Set user-defined property "INIT =  0" for instance <INST_BW_FD1> in unit <sram_ctrl>.
    Set user-defined property "INIT =  0" for instance <INST_BW_FD2> in unit <sram_ctrl>.
    Set user-defined property "INIT =  0" for instance <INST_BW_FD3> in unit <sram_ctrl>.
Analyzing module <sram_read_clock> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_read_clock> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <ibuf> in unit <sram_read_clock>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <ibuf> in unit <sram_read_clock>.
    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <ibuf> in unit <sram_read_clock>.
    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <ibuf> in unit <sram_read_clock>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <ibuf> in unit <sram_read_clock>.
WARNING:Xst:37 - Detected unknown constraint/property "SYN_USEIOFF". This constraint/property is not supported by the current software release and will be ignored.
Analyzing module <sram_read_dcm> in library <work>.
Module <sram_read_dcm> is correct for synthesis.
 
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLKIN_PERIOD =  8.000000" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  FIXED" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "PHASE_SHIFT =  -32" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "SIM_MODE =  SAFE" for instance <DCM_INST> in unit <sram_read_dcm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <sram_read_dcm>.
Analyzing module <sram_address> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_address> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <AD_FDC_W_bar> in unit <sram_address>.
    Set user-defined property "INIT =  0" for instance <AD_FDC_D2> in unit <sram_address>.
    Set user-defined property "INIT =  0" for instance <AD_FDDR_DA> in unit <sram_address>.
    Set user-defined property "INIT =  0" for instance <AD_FDDR_DQ> in unit <sram_address>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <AD_FDDR_AOBUF> in unit <sram_address>.
    Set user-defined property "DRIVE =  12" for instance <AD_FDDR_AOBUF> in unit <sram_address>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <AD_FDDR_AOBUF> in unit <sram_address>.
    Set user-defined property "SLEW =  SLOW" for instance <AD_FDDR_AOBUF> in unit <sram_address>.
Analyzing module <sram_write> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_write> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <FDC_ENVOI> in unit <sram_write>.
    Set user-defined property "INIT =  0" for instance <WRT_FDC_D1> in unit <sram_write>.
    Set user-defined property "INIT =  0" for instance <WRT_FDDR_DQ> in unit <sram_write>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <WRT_FDDR_DOBUFT> in unit <sram_write>.
    Set user-defined property "DRIVE =  12" for instance <WRT_FDDR_DOBUFT> in unit <sram_write>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <WRT_FDDR_DOBUFT> in unit <sram_write>.
    Set user-defined property "SLEW =  SLOW" for instance <WRT_FDDR_DOBUFT> in unit <sram_write>.
Analyzing module <sram_read_new> in library <work>.
	GND = 1'b0
	VCC = 1'b1
Module <sram_read_new> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <RD_FDC_D0_C_RLMT> in unit <sram_read_new>.
    Set user-defined property "INIT =  0" for instance <RD_FDC_DX0_K> in unit <sram_read_new>.
    Set user-defined property "INIT =  0" for instance <RD_FDC_DX1_K> in unit <sram_read_new>.
    Set user-defined property "INIT =  0" for instance <RD_FDC_D0_K> in unit <sram_read_new>.
    Set user-defined property "INIT =  0" for instance <RD_FDC_D1_K> in unit <sram_read_new>.
    Set user-defined property "KEEP =  true" for signal <Q0> in unit <sram_read_new>.
    Set user-defined property "KEEP =  true" for signal <Q1> in unit <sram_read_new>.
    Set user-defined property "KEEP =  true" for signal <QX0>.
    Set user-defined property "KEEP =  true" for signal <QX1>.
Analyzing module <mdio> in library <work>.
	ADDR_MDIO_BUSY = 8'b00000101
	ADDR_MDIO_DATA = 8'b00000100
	ADDR_MDIO_ERROR = 8'b00000110
	ADDR_MDIO_OPCODE = 8'b00000001
	ADDR_MDIO_PHY_ADDR = 8'b00000010
	ADDR_MDIO_REG_ADDR = 8'b00000011
	ADDR_MDIO_SEL = 8'b00000000
	ADDR_MDIO_START = 8'b00000111
	Calling function <MuxBusDataRead>.
Module <mdio> is correct for synthesis.
 
Analyzing module <mdio_fsm> in library <work>.
	STATE_DATA_READ = 3'b110
	STATE_DATA_WRITE = 3'b111
	STATE_IDLE = 3'b000
	STATE_OPCODE = 3'b010
	STATE_PHY_ADDR = 3'b011
	STATE_REG_ADDR = 3'b100
	STATE_START = 3'b001
	STATE_TA = 3'b101
Module <mdio_fsm> is correct for synthesis.
 
Analyzing module <sfp> in library <work>.
	ADDR_IIC_BUSY = 8'b00000101
	ADDR_IIC_DATA = 8'b00000100
	ADDR_IIC_ERROR = 8'b00000110
	ADDR_IIC_REG_ADDR = 8'b00000011
	ADDR_IIC_RW = 8'b00000001
	ADDR_IIC_SEL = 8'b00000000
	ADDR_IIC_SLAVE_ADDR = 8'b00000010
	ADDR_IIC_START = 8'b00000111
	ADDR_SFP0_ALS_ENABLE = 8'b00001110
	ADDR_SFP0_LOS = 8'b00001010
	ADDR_SFP0_MASK = 8'b00001101
	ADDR_SFP0_PRESENT = 8'b00001100
	ADDR_SFP0_RATE_SEL = 8'b00001011
	ADDR_SFP0_TX_DISABLE = 8'b00001000
	ADDR_SFP0_TX_FAULT = 8'b00001001
	ADDR_SFP1_ALS_ENABLE = 8'b00010110
	ADDR_SFP1_LOS = 8'b00010010
	ADDR_SFP1_MASK = 8'b00010101
	ADDR_SFP1_PRESENT = 8'b00010100
	ADDR_SFP1_RATE_SEL = 8'b00010011
	ADDR_SFP1_TX_DISABLE = 8'b00010000
	ADDR_SFP1_TX_FAULT = 8'b00010001
	ADDR_SFP2_ALS_ENABLE = 8'b00011110
	ADDR_SFP2_LOS = 8'b00011010
	ADDR_SFP2_MASK = 8'b00011101
	ADDR_SFP2_PRESENT = 8'b00011100
	ADDR_SFP2_RATE_SEL = 8'b00011011
	ADDR_SFP2_TX_DISABLE = 8'b00011000
	ADDR_SFP2_TX_FAULT = 8'b00011001
	ADDR_SFP3_ALS_ENABLE = 8'b00100110
	ADDR_SFP3_LOS = 8'b00100010
	ADDR_SFP3_MASK = 8'b00100101
	ADDR_SFP3_PRESENT = 8'b00100100
	ADDR_SFP3_RATE_SEL = 8'b00100011
	ADDR_SFP3_TX_DISABLE = 8'b00100000
	ADDR_SFP3_TX_FAULT = 8'b00100001
	Calling function <MuxBusDataRead>.
Module <sfp> is correct for synthesis.
 
Analyzing module <iic_state_machine> in library <work>.
	IIC_CLOCK_PERIOD = 12'b001001011000
	STATE_ACK_MASTER = 4'b0100
	STATE_ACK_SLAVE = 4'b0011
	STATE_ADDR = 4'b0101
	STATE_DEVSEL_RW = 4'b0010
	STATE_PAUSE = 4'b0000
	STATE_RECEIVE = 4'b0110
	STATE_START = 4'b0001
	STATE_STOP = 4'b1000
	STATE_TRANSMIT = 4'b0111
Module <iic_state_machine> is correct for synthesis.
 
Analyzing module <sfp_irq> in library <work>.
Module <sfp_irq> is correct for synthesis.
 
Analyzing module <one_sfp_irq> in library <work>.
Module <one_sfp_irq> is correct for synthesis.
 
Analyzing module <sfp_als> in library <work>.
Module <sfp_als> is correct for synthesis.
 
Analyzing module <one_sfp_als> in library <work>.
	CLKDIV_RESET_BIT = 32'sb00000000000000000000000000000010
	DELAY_BIT = 32'sb00000000000000000000000000000111
	LOSS_BIT = 32'sb00000000000000000000000000000011
	STABLE_BIT = 32'sb00000000000000000000000000000011
	STATE_DELAY = 3'b010
	STATE_IDLE = 3'b000
	STATE_LOSS = 3'b001
	STATE_TRYLASERON = 3'b011
	TRYLASER_BIT = 32'sb00000000000000000000000000000101
Module <one_sfp_als> is correct for synthesis.
 
Analyzing module <phy_new> in library <work>.
	ADDR_PHY0_CONF_0 = 8'b00010000
	ADDR_PHY0_CONF_1 = 8'b00010001
	ADDR_PHY0_CONF_2 = 8'b00010010
	ADDR_PHY0_CONF_3 = 8'b00010011
	ADDR_PHY0_CONF_4 = 8'b00010100
	ADDR_PHY1_CONF_0 = 8'b00011000
	ADDR_PHY1_CONF_1 = 8'b00011001
	ADDR_PHY1_CONF_2 = 8'b00011010
	ADDR_PHY1_CONF_3 = 8'b00011011
	ADDR_PHY1_CONF_4 = 8'b00011100
	ADDR_PHY2_CONF_0 = 8'b00100000
	ADDR_PHY2_CONF_1 = 8'b00100001
	ADDR_PHY2_CONF_2 = 8'b00100010
	ADDR_PHY2_CONF_3 = 8'b00100011
	ADDR_PHY2_CONF_4 = 8'b00100100
	ADDR_PHY3_CONF_0 = 8'b00101000
	ADDR_PHY3_CONF_1 = 8'b00101001
	ADDR_PHY3_CONF_2 = 8'b00101010
	ADDR_PHY3_CONF_3 = 8'b00101011
	ADDR_PHY3_CONF_4 = 8'b00101100
	ADDR_PHY_CONF_0 = 8'b00001000
	ADDR_PHY_CONF_1 = 8'b00001001
	ADDR_PHY_RESET = 8'b00000000
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
	Calling function <Alu>.
Module <phy_new> is correct for synthesis.
 
Analyzing module <reset_gen> in library <work>.
	STATE_NORMAL = 1'b1
	STATE_RESET = 1'b0
Module <reset_gen> is correct for synthesis.
 
Analyzing module <timer> in library <work>.
	ADDR_DEVELOPER = 8'b00100000
	ADDR_FIRMVARE_NAME = 8'b00011000
	ADDR_FIRMVARE_VER = 8'b00011001
	ADDR_FPGA_LCELS = 8'b00001001
	ADDR_FPGA_SERIES = 8'b00001000
	ADDR_FPGA_SPEED = 8'b00001010
	ADDR_MICROSECOND = 8'b00000001
	ADDR_PRODUCER = 8'b00010000
	ADDR_SECOND = 8'b00000000
	DEVELOPER = 32'b01000110010101010100001101001011
	FIRMVARE_NAME = 32'b01001101010000010100001100100000
	FIRMVARE_VER = 32'b00110000001100000011000000110001
	FPGA_LCELS = 32'b00110100001100000011000000110000
	FPGA_SERIES = 32'b01011000010000110011001101010011
	FPGA_SPEED = 32'b00110100010000110010000000100000
	PRODUCER = 32'b01010010010010010100111001000001
	Calling function <MuxInt>.
Module <timer> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <i> in unit <mac_rx_ff_write> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_rx_ff_write> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_rx_ff_read> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_rx_ff_read> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_tx_ff> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_tx_ff> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_tx_ff> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <i> in unit <mac_tx_ff> has a constant value of 11111111111111111111111111111111 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <TxRa> in unit <bus> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Error> in unit <mdio_fsm> has a constant value of 0 during circuit operation. The register is replaced by logic.

Synthesizing Unit <spi_to_epc>.
    Related source file is "src/other_src/spi_to_epc.v".
WARNING:Xst:647 - Input <Clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <SlaveAddr<6:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_0> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 15                                             |
    | Inputs             | 4                                              |
    | Outputs            | 8                                              |
    | Clock              | SpiSclk                   (rising_edge)        |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <SpiMiso>.
    Found 1-bit 32-to-1 multiplexer for signal <$varindex0000> created at line 139.
    Found 5-bit register for signal <BitCount>.
    Found 5-bit adder for signal <BitCount$share0000> created at line 64.
    Found 1-of-8 decoder for signal <Decoder/1/Decoder>.
    Found 32-bit 8-to-1 multiplexer for signal <Mux/1/Mux>.
    Found 1-bit register for signal <Read>.
    Found 32-bit register for signal <ReceiveData>.
    Found 8-bit register for signal <RegAddr>.
    Found 1-bit register for signal <SlaveAddr<7>>.
    Found 3-bit register for signal <SlaveAddr<2:0>>.
    Found 5-bit comparator less for signal <State$cmp_lt0000> created at line 83.
    Found 5-bit comparator less for signal <State$cmp_lt0001> created at line 111.
    Found 1-bit register for signal <Write>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  52 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  33 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <spi_to_epc> synthesized.


Synthesizing Unit <timer>.
    Related source file is "src/other_src/timer.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit up counter for signal <Second>.
    Found 32-bit register for signal <Microsecond>.
    Found 32-bit register for signal <LoadMicrosecond>.
    Found 32-bit register for signal <LoadSecond>.
    Found 32-bit adder for signal <Microsecond$addsub0000> created at line 108.
    Found 32-bit 4-to-1 multiplexer for signal <Microsecond$mux0000>.
    Found 32-bit comparator less for signal <Second$cmp_lt0000> created at line 107.
    Summary:
	inferred   1 Counter(s).
	inferred  96 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
	inferred  32 Multiplexer(s).
Unit <timer> synthesized.


Synthesizing Unit <mac_bus_mux>.
    Related source file is "src/mac_buf_src/mac_bus_mux.v".
Unit <mac_bus_mux> synthesized.


Synthesizing Unit <port_regs_1>.
    Related source file is "src/mac_buf_src/port_regs.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <PortAcceptFrameType>.
    Found 3-bit register for signal <MacSrcFilterNum>.
    Found 3-bit register for signal <MacDstFilterNum>.
    Found 3-bit register for signal <PortPriority>.
    Found 24-bit register for signal <PortTrafficClassMap>.
    Found 1-bit register for signal <MacReset>.
    Found 24-bit register for signal <PortIngressPriorityMap>.
    Found 3-bit register for signal <PortState>.
    Found 1-bit register for signal <MacSrcFilterEna>.
    Found 1-bit register for signal <MacDstFilterEna>.
    Found 4-bit register for signal <PortNumber>.
    Found 48-bit register for signal <MacDst0Filter>.
    Found 48-bit register for signal <MacDst0FilterMask>.
    Found 48-bit register for signal <MacDst1Filter>.
    Found 48-bit register for signal <MacDst1FilterMask>.
    Found 48-bit register for signal <MacDst2Filter>.
    Found 48-bit register for signal <MacDst2FilterMask>.
    Found 48-bit register for signal <MacDst3Filter>.
    Found 48-bit register for signal <MacDst3FilterMask>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/1/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/2/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/3/MacMux>.
    Found 4-bit comparator less for signal <MacReset$cmp_lt0000> created at line 280.
    Found 4-bit up counter for signal <MacResetCount>.
    Found 4-bit comparator greatequal for signal <MacResetCount$cmp_ge0000> created at line 280.
    Found 48-bit register for signal <MacSrc0Filter>.
    Found 48-bit register for signal <MacSrc1Filter>.
    Found 48-bit register for signal <MacSrc2Filter>.
    Found 48-bit register for signal <MacSrc3Filter>.
    Found 48-bit register for signal <MacSrc4Filter>.
    Found 48-bit register for signal <MacSrc5Filter>.
    Found 48-bit register for signal <MacSrc6Filter>.
    Found 48-bit register for signal <MacSrc7Filter>.
    Summary:
	inferred   1 Counter(s).
	inferred 832 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 144 Multiplexer(s).
Unit <port_regs_1> synthesized.


Synthesizing Unit <phy_int_new>.
    Related source file is "src/mac_src/phy_int_new.v".
WARNING:Xst:647 - Input <Speed<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <Col_dl1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit register for signal <MRxD>.
    Found 1-bit register for signal <MCrs_dv>.
    Found 1-bit register for signal <Tx_en>.
    Found 8-bit register for signal <Txd>.
    Found 1-bit register for signal <Crs_dl1>.
    Found 8-bit register for signal <MTxD_dl1>.
    Found 1-bit register for signal <MTxEn_dl1>.
    Found 1-bit register for signal <Rx_dv_dl1>.
    Found 1-bit register for signal <Rx_dv_dl2>.
    Found 1-bit register for signal <Rx_er_dl1>.
    Found 1-bit register for signal <Rx_odd_data_ptr>.
    Found 8-bit register for signal <Rxd_dl1>.
    Found 8-bit register for signal <Rxd_dl2>.
    Found 1-bit register for signal <Tx_odd_data_ptr>.
    Summary:
	inferred  49 D-type flip-flop(s).
Unit <phy_int_new> synthesized.


Synthesizing Unit <short_impulse>.
    Related source file is "src/other_src/short_impulse.v".
    Found 1-bit register for signal <a>.
    Found 1-bit register for signal <b>.
    Found 1-bit register for signal <c>.
    Found 1-bit xor2 for signal <Out$xor0000> created at line 30.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <short_impulse> synthesized.


Synthesizing Unit <clock_div>.
    Related source file is "src/mac_src/tech/clock_div.v".
    Found 1-bit register for signal <Out>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <clock_div> synthesized.


Synthesizing Unit <clock_switch>.
    Related source file is "src/mac_src/tech/clock_switch.v".
Unit <clock_switch> synthesized.


Synthesizing Unit <mac_rx_ctrl>.
    Related source file is "src/mac_src/mac_rx/mac_rx_ctrl.v".
    Found finite state machine <FSM_1> for signal <Current_state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 32                                             |
    | Inputs             | 11                                             |
    | Outputs            | 32                                             |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | Clk_ena                   (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <Pause_current>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 27                                             |
    | Inputs             | 18                                             |
    | Outputs            | 3                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | Clk_ena                   (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Rx_apply_rmon>.
    Found 1-bit register for signal <pause_quanta_val>.
    Found 3-bit register for signal <Rx_pkt_err_type_rmon>.
    Found 3-bit register for signal <Rx_pkt_type_rmon>.
    Found 16-bit register for signal <pause_quanta>.
    Found 16-bit subtractor for signal <Rx_pkt_length_rmon>.
    Found 1-bit register for signal <broadcast_ptr>.
    Found 8-bit subtractor for signal <$sub0000> created at line 195.
    Found 1-bit register for signal <Crs_dv>.
    Found 8-bit comparator equal for signal <Current_state$cmp_eq0002> created at line 195.
    Found 16-bit up counter for signal <Frame_length_counter>.
    Found 6-bit up counter for signal <IFG_counter>.
    Found 16-bit comparator greatequal for signal <MAC_add_en$cmp_ge0000> created at line 346.
    Found 16-bit comparator lessequal for signal <MAC_add_en$cmp_le0000> created at line 346.
    Found 1-bit register for signal <pause_frame_ptr>.
    Found 8-bit register for signal <pause_quanta_h>.
    Found 1-bit register for signal <pause_quanta_val_tmp>.
    Found 1-bit register for signal <Rx_apply_rmon_tmp>.
    Found 1-bit register for signal <Rx_apply_rmon_tmp_pl1>.
    Found 8-bit register for signal <RxD>.
    Found 8-bit register for signal <RxD_dl1>.
    Found 1-bit register for signal <RxErr>.
    Found 16-bit comparator greater for signal <Too_long$cmp_gt0000> created at line 274.
    Found 16-bit comparator less for signal <Too_short$cmp_lt0000> created at line 268.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  55 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   5 Comparator(s).
Unit <mac_rx_ctrl> synthesized.


Synthesizing Unit <broadcast_filter>.
    Related source file is "src/mac_src/mac_rx/broadcast_filter.v".
    Found 1-bit register for signal <broadcast_drop>.
    Found 16-bit up counter for signal <broadcast_counter>.
    Found 16-bit comparator equal for signal <broadcast_counter$cmp_eq0000> created at line 40.
    Found 16-bit comparator not equal for signal <broadcast_counter$cmp_ne0000> created at line 38.
    Found 16-bit up counter for signal <time_counter>.
    Found 16-bit comparator equal for signal <time_counter$cmp_eq0000> created at line 28.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <broadcast_filter> synthesized.


Synthesizing Unit <crc_chk>.
    Related source file is "src/mac_src/mac_rx/crc_chk.v".
    Found 32-bit register for signal <CRC_reg>.
    Found 1-bit xor2 for signal <CRC_reg$xor0000> created at line 72.
    Found 1-bit xor3 for signal <CRC_reg$xor0001> created at line 71.
    Found 1-bit xor4 for signal <CRC_reg$xor0002> created at line 70.
    Found 1-bit xor4 for signal <CRC_reg$xor0003> created at line 69.
    Found 1-bit xor4 for signal <CRC_reg$xor0004> created at line 68.
    Found 1-bit xor4 for signal <CRC_reg$xor0005> created at line 67.
    Found 1-bit xor3 for signal <CRC_reg$xor0006> created at line 66.
    Found 1-bit xor3 for signal <CRC_reg$xor0007> created at line 65.
    Found 1-bit xor3 for signal <CRC_reg$xor0008> created at line 64.
    Found 1-bit xor2 for signal <CRC_reg$xor0009> created at line 63.
    Found 1-bit xor2 for signal <CRC_reg$xor0010> created at line 62.
    Found 1-bit xor2 for signal <CRC_reg$xor0011> created at line 61.
    Found 1-bit xor3 for signal <CRC_reg$xor0012> created at line 60.
    Found 1-bit xor4 for signal <CRC_reg$xor0013> created at line 59.
    Found 1-bit xor4 for signal <CRC_reg$xor0014> created at line 58.
    Found 1-bit xor4 for signal <CRC_reg$xor0015> created at line 57.
    Found 1-bit xor4 for signal <CRC_reg$xor0016> created at line 56.
    Found 1-bit xor4 for signal <CRC_reg$xor0017> created at line 55.
    Found 1-bit xor6 for signal <CRC_reg$xor0018> created at line 54.
    Found 1-bit xor6 for signal <CRC_reg$xor0019> created at line 53.
    Found 1-bit xor4 for signal <CRC_reg$xor0020> created at line 52.
    Found 1-bit xor3 for signal <CRC_reg$xor0021> created at line 51.
    Found 1-bit xor3 for signal <CRC_reg$xor0022> created at line 50.
    Found 1-bit xor3 for signal <CRC_reg$xor0023> created at line 49.
    Found 1-bit xor3 for signal <CRC_reg$xor0024> created at line 48.
    Found 1-bit xor4 for signal <CRC_reg$xor0025> created at line 47.
    Found 1-bit xor4 for signal <CRC_reg$xor0026> created at line 46.
    Found 1-bit xor4 for signal <CRC_reg$xor0027> created at line 45.
    Found 1-bit xor3 for signal <CRC_reg$xor0028> created at line 44.
    Found 1-bit xor3 for signal <CRC_reg$xor0029> created at line 43.
    Found 1-bit xor3 for signal <CRC_reg$xor0030> created at line 42.
    Found 1-bit xor2 for signal <CRC_reg$xor0031> created at line 41.
    Found 1-bit xor2 for signal <CRC_reg$xor0032> created at line 72.
    Found 1-bit xor2 for signal <CRC_reg$xor0033> created at line 71.
    Found 1-bit xor2 for signal <CRC_reg$xor0034> created at line 71.
    Found 1-bit xor2 for signal <CRC_reg$xor0035> created at line 70.
    Found 1-bit xor2 for signal <CRC_reg$xor0036> created at line 70.
    Found 1-bit xor2 for signal <CRC_reg$xor0037> created at line 69.
    Found 1-bit xor2 for signal <CRC_reg$xor0038> created at line 68.
    Found 1-bit xor2 for signal <CRC_reg$xor0040> created at line 67.
    Found 1-bit xor2 for signal <CRC_reg$xor0044> created at line 64.
    Found 1-bit xor2 for signal <CRC_reg$xor0045> created at line 63.
    Found 1-bit xor2 for signal <CRC_reg$xor0050> created at line 56.
    Found 1-bit xor2 for signal <CRC_reg$xor0052> created at line 55.
    Found 1-bit xor2 for signal <CRC_reg$xor0058> created at line 53.
    Found 1-bit xor2 for signal <CRC_reg$xor0060> created at line 52.
    Found 1-bit xor2 for signal <CRC_reg$xor0061> created at line 51.
    Found 1-bit xor2 for signal <CRC_reg$xor0065> created at line 47.
    Found 1-bit xor2 for signal <CRC_reg$xor0067> created at line 46.
    Found 1-bit xor2 for signal <CRC_reg$xor0071> created at line 44.
    Found 1-bit xor2 for signal <CRC_reg$xor0072> created at line 43.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred  27 Xor(s).
Unit <crc_chk> synthesized.


Synthesizing Unit <mac_rx_ff_write>.
    Related source file is "src/mac_src/mac_rx/mac_rx_ff_write.v".
    Found finite state machine <FSM_3> for signal <Current_state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 23                                             |
    | Inputs             | 3                                              |
    | Outputs            | 12                                             |
    | Clock              | Clk_MAC                   (rising_edge)        |
    | Clock enable       | Clk_MAC_ena               (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 1001                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit register for signal <Add_wr_gray>.
    Found 36-bit register for signal <Din>.
    Found 1-bit register for signal <Wr_en>.
    Found 1-bit register for signal <Packet_number_add>.
    Found 1-bit register for signal <Add_wr_jump>.
    Found 9-bit up counter for signal <Add_wr>.
    Found 1-bit register for signal <Fifo_full>.
    Found 9-bit register for signal <Add_rd_gray_dl1>.
    Found 9-bit register for signal <Add_rd_ungray>.
    Found 1-bit xor2 for signal <Add_rd_ungray_0$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_0$xor0001> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_1$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_2$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_3$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_4$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_5$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_rd_ungray_6$xor0000> created at line 336.
    Found 1-bit xor2 for signal <Add_wr_gray_0$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_1$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_2$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_3$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_4$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_5$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_6$xor0000> created at line 292.
    Found 1-bit xor2 for signal <Add_wr_gray_7$xor0000> created at line 292.
    Found 1-bit register for signal <Add_wr_jump_tmp>.
    Found 1-bit register for signal <Add_wr_jump_tmp_pl1>.
    Found 9-bit adder for signal <Add_wr_pluse>.
    Found 9-bit adder for signal <Add_wr_pluse2>.
    Found 9-bit adder for signal <Add_wr_pluse3>.
    Found 9-bit adder for signal <Add_wr_pluse4>.
    Found 9-bit register for signal <Add_wr_reg>.
    Found 32-bit register for signal <Din_tmp_reg>.
    Found 8-bit register for signal <Fifo_data_byte1>.
    Found 8-bit register for signal <Fifo_data_byte2>.
    Found 8-bit register for signal <Fifo_data_byte3>.
    Found 8-bit register for signal <Fifo_data_dl1>.
    Found 1-bit register for signal <Fifo_data_en_dl1>.
    Found 9-bit comparator equal for signal <Fifo_full$cmp_eq0000> created at line 348.
    Found 9-bit comparator equal for signal <Fifo_full$cmp_eq0001> created at line 348.
    Found 9-bit comparator equal for signal <Fifo_full$cmp_eq0002> created at line 348.
    Found 1-bit register for signal <Full>.
    Found 9-bit comparator equal for signal <Full$cmp_eq0000> created at line 232.
    Found 1-bit register for signal <Packet_number_add_tmp>.
    Found 1-bit register for signal <Packet_number_add_tmp_dl1>.
    Found 1-bit register for signal <Packet_number_add_tmp_dl2>.
    Found 1-bit register for signal <Wr_en_ptr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred 148 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <mac_rx_ff_write> synthesized.


Synthesizing Unit <mac_rx_ff_read>.
    Related source file is "src/mac_src/mac_rx/mac_rx_ff_read.v".
WARNING:Xst:646 - Signal <Dout_dl1<34>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_4> for signal <Current_state_SYS>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk_SYS                   (rising_edge)        |
    | Clock enable       | Clk_SYS_ena               (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 011                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Rx_mac_pa>.
    Found 1-bit register for signal <Rx_mac_sop>.
    Found 1-bit register for signal <Rx_mac_ra>.
    Found 9-bit up counter for signal <Add_rd>.
    Found 9-bit register for signal <Add_rd_gray>.
    Found 1-bit xor2 for signal <Add_rd_gray_0$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_1$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_2$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_3$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_4$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_5$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_6$xor0000> created at line 224.
    Found 1-bit xor2 for signal <Add_rd_gray_7$xor0000> created at line 224.
    Found 9-bit register for signal <Add_wr_gray_dl1>.
    Found 1-bit register for signal <Add_wr_jump_rd_pl1>.
    Found 9-bit register for signal <Add_wr_ungray>.
    Found 1-bit xor2 for signal <Add_wr_ungray_0$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_0$xor0001> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_1$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_2$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_3$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_4$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_5$xor0000> created at line 247.
    Found 1-bit xor2 for signal <Add_wr_ungray_6$xor0000> created at line 247.
    Found 36-bit register for signal <Dout_dl1>.
    Found 1-bit register for signal <Empty>.
    Found 9-bit comparator equal for signal <Empty$cmp_eq0000> created at line 256.
    Found 5-bit register for signal <Fifo_data_count>.
    Found 5-bit subtractor for signal <Fifo_data_count$sub0000> created at line 186.
    Found 1-bit register for signal <Packet_number_add_dl1>.
    Found 1-bit register for signal <Packet_number_add_dl2>.
    Found 6-bit updown counter for signal <Packet_number_inFF>.
    Found 5-bit register for signal <Rx_Hwmark_pl>.
    Found 5-bit register for signal <Rx_Lwmark_pl>.
    Found 1-bit register for signal <Rx_mac_pa_tmp>.
    Found 5-bit comparator greater for signal <Rx_mac_ra$cmp_gt0000> created at line 202.
    Found 5-bit comparator lessequal for signal <Rx_mac_ra$cmp_le0000> created at line 202.
    Found 6-bit comparator less for signal <Rx_mac_ra$cmp_lt0000> created at line 204.
    Found 5-bit comparator less for signal <Rx_mac_ra$cmp_lt0001> created at line 204.
    Found 1-bit register for signal <Rx_mac_sop_tmp>.
    Found 1-bit register for signal <Rx_mac_sop_tmp_dl1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  88 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   5 Comparator(s).
Unit <mac_rx_ff_read> synthesized.


Synthesizing Unit <mac_tx_ctrl>.
    Related source file is "src/mac_src/mac_tx/mac_tx_ctrl.v".
WARNING:Xst:647 - Input <Fifo_da> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_5> for signal <Current_state>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 70                                             |
    | Inputs             | 20                                             |
    | Outputs            | 42                                             |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | Clk_ena                   (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 1101                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <xon_gen_complete>.
    Found 1-bit register for signal <MAC_tx_addr_rd>.
    Found 1-bit register for signal <Tx_apply_rmon>.
    Found 1-bit register for signal <pause_quanta_sub>.
    Found 1-bit register for signal <xoff_gen_complete>.
    Found 8-bit register for signal <TxD>.
    Found 4-bit up counter for signal <RetryCnt>.
    Found 16-bit up counter for signal <Tx_pkt_length_rmon>.
    Found 3-bit register for signal <Tx_pkt_type_rmon>.
    Found 3-bit register for signal <Tx_pkt_err_type_rmon>.
    Found 1-bit register for signal <TxEn>.
    Found 8-bit subtractor for signal <$sub0000> created at line 191.
    Found 8-bit comparator equal for signal <Current_state$cmp_eq0000> created at line 191.
    Found 8-bit comparator greatequal for signal <Current_state$cmp_ge0000> created at line 233.
    Found 4-bit comparator greater for signal <Current_state$cmp_gt0000> created at line 249.
    Found 4-bit comparator lessequal for signal <Current_state$cmp_le0000> created at line 247.
    Found 6-bit up counter for signal <IFG_counter>.
    Found 8-bit up counter for signal <IPLengthCounter>.
    Found 8-bit up counter for signal <JamCounter>.
    Found 1-bit register for signal <MAC_header_slot>.
    Found 1-bit register for signal <MAC_header_slot_tmp>.
    Found 16-bit comparator greatequal for signal <MAC_tx_addr_rd$cmp_ge0000> created at line 535.
    Found 16-bit comparator lessequal for signal <MAC_tx_addr_rd$cmp_le0000> created at line 535.
    Found 2-bit up counter for signal <PADCounter>.
    Found 8-bit up counter for signal <pause_counter>.
    Found 1-bit register for signal <pause_frame_send_en_dl1>.
    Found 16-bit register for signal <pause_quanta_set_dl1>.
    Found 1-bit register for signal <PktDrpEvenPtr>.
    Found 5-bit up counter for signal <Preamble_counter>.
    Found 16-bit comparator greatequal for signal <Src_MAC_ptr$cmp_ge0000> created at line 525.
    Found 16-bit comparator lessequal for signal <Src_MAC_ptr$cmp_le0000> created at line 525.
    Found 1-bit register for signal <Tx_apply_rmon_tmp>.
    Found 1-bit register for signal <Tx_apply_rmon_tmp_pl1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   8 Counter(s).
	inferred  42 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   8 Comparator(s).
Unit <mac_tx_ctrl> synthesized.


Synthesizing Unit <crc_gen>.
    Related source file is "src/mac_src/mac_tx/crc_gen.v".
    Found 4-bit up counter for signal <Counter>.
    Found 32-bit register for signal <CRC_reg>.
    Found 32-bit 4-to-1 multiplexer for signal <CRC_reg$mux0000>.
    Found 1-bit xor2 for signal <CRC_reg$xor0000> created at line 108.
    Found 1-bit xor3 for signal <CRC_reg$xor0001> created at line 107.
    Found 1-bit xor4 for signal <CRC_reg$xor0002> created at line 106.
    Found 1-bit xor4 for signal <CRC_reg$xor0003> created at line 105.
    Found 1-bit xor4 for signal <CRC_reg$xor0004> created at line 104.
    Found 1-bit xor4 for signal <CRC_reg$xor0005> created at line 103.
    Found 1-bit xor3 for signal <CRC_reg$xor0006> created at line 102.
    Found 1-bit xor3 for signal <CRC_reg$xor0007> created at line 101.
    Found 1-bit xor3 for signal <CRC_reg$xor0008> created at line 100.
    Found 1-bit xor2 for signal <CRC_reg$xor0009> created at line 99.
    Found 1-bit xor2 for signal <CRC_reg$xor0010> created at line 98.
    Found 1-bit xor2 for signal <CRC_reg$xor0011> created at line 97.
    Found 1-bit xor3 for signal <CRC_reg$xor0012> created at line 96.
    Found 1-bit xor4 for signal <CRC_reg$xor0013> created at line 95.
    Found 1-bit xor4 for signal <CRC_reg$xor0014> created at line 94.
    Found 1-bit xor4 for signal <CRC_reg$xor0015> created at line 93.
    Found 1-bit xor4 for signal <CRC_reg$xor0016> created at line 92.
    Found 1-bit xor4 for signal <CRC_reg$xor0017> created at line 91.
    Found 1-bit xor6 for signal <CRC_reg$xor0018> created at line 90.
    Found 1-bit xor6 for signal <CRC_reg$xor0019> created at line 89.
    Found 1-bit xor4 for signal <CRC_reg$xor0020> created at line 88.
    Found 1-bit xor3 for signal <CRC_reg$xor0021> created at line 87.
    Found 1-bit xor3 for signal <CRC_reg$xor0022> created at line 86.
    Found 1-bit xor3 for signal <CRC_reg$xor0023> created at line 85.
    Found 1-bit xor3 for signal <CRC_reg$xor0024> created at line 84.
    Found 1-bit xor4 for signal <CRC_reg$xor0025> created at line 83.
    Found 1-bit xor4 for signal <CRC_reg$xor0026> created at line 82.
    Found 1-bit xor4 for signal <CRC_reg$xor0027> created at line 81.
    Found 1-bit xor3 for signal <CRC_reg$xor0028> created at line 80.
    Found 1-bit xor3 for signal <CRC_reg$xor0029> created at line 79.
    Found 1-bit xor3 for signal <CRC_reg$xor0030> created at line 78.
    Found 1-bit xor2 for signal <CRC_reg$xor0031> created at line 77.
    Found 1-bit xor2 for signal <CRC_reg$xor0032> created at line 108.
    Found 1-bit xor2 for signal <CRC_reg$xor0033> created at line 107.
    Found 1-bit xor2 for signal <CRC_reg$xor0034> created at line 107.
    Found 1-bit xor2 for signal <CRC_reg$xor0035> created at line 106.
    Found 1-bit xor2 for signal <CRC_reg$xor0036> created at line 106.
    Found 1-bit xor2 for signal <CRC_reg$xor0037> created at line 105.
    Found 1-bit xor2 for signal <CRC_reg$xor0038> created at line 104.
    Found 1-bit xor2 for signal <CRC_reg$xor0040> created at line 103.
    Found 1-bit xor2 for signal <CRC_reg$xor0044> created at line 100.
    Found 1-bit xor2 for signal <CRC_reg$xor0045> created at line 99.
    Found 1-bit xor2 for signal <CRC_reg$xor0050> created at line 92.
    Found 1-bit xor2 for signal <CRC_reg$xor0052> created at line 91.
    Found 1-bit xor2 for signal <CRC_reg$xor0058> created at line 89.
    Found 1-bit xor2 for signal <CRC_reg$xor0060> created at line 88.
    Found 1-bit xor2 for signal <CRC_reg$xor0061> created at line 87.
    Found 1-bit xor2 for signal <CRC_reg$xor0065> created at line 83.
    Found 1-bit xor2 for signal <CRC_reg$xor0067> created at line 82.
    Found 1-bit xor2 for signal <CRC_reg$xor0071> created at line 80.
    Found 1-bit xor2 for signal <CRC_reg$xor0072> created at line 79.
    Summary:
	inferred   1 Counter(s).
	inferred  32 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
	inferred  27 Xor(s).
Unit <crc_gen> synthesized.


Synthesizing Unit <flow_ctrl>.
    Related source file is "src/mac_src/mac_tx/flow_ctrl.v".
    Found 1-bit register for signal <xon_gen>.
    Found 1-bit register for signal <xoff_gen>.
    Found 1-bit register for signal <pause_apply>.
    Found 16-bit down counter for signal <pause_quanta_counter>.
    Found 16-bit register for signal <pause_quanta_dl1>.
    Found 1-bit register for signal <pause_quanta_val_dl1>.
    Found 1-bit register for signal <pause_quanta_val_dl2>.
    Found 1-bit register for signal <tx_pause_en_dl1>.
    Found 1-bit register for signal <tx_pause_en_dl2>.
    Found 1-bit register for signal <xoff_cpu_dl1>.
    Found 1-bit register for signal <xoff_cpu_dl2>.
    Found 1-bit register for signal <xon_cpu_dl1>.
    Found 1-bit register for signal <xon_cpu_dl2>.
    Summary:
	inferred   1 Counter(s).
	inferred  27 D-type flip-flop(s).
Unit <flow_ctrl> synthesized.


Synthesizing Unit <ramdon_gen>.
    Related source file is "src/mac_src/mac_tx/ramdon_gen.v".
    Found 1-bit register for signal <Random_time_meet>.
    Found 10-bit down counter for signal <Ramdom_counter>.
    Found 10-bit register for signal <Random_sequence>.
    Found 1-bit xor2 for signal <Random_sequence$xor0000> created at line 28.
    Found 8-bit up counter for signal <Slot_time_counter>.
    Summary:
	inferred   2 Counter(s).
	inferred  11 D-type flip-flop(s).
Unit <ramdon_gen> synthesized.


Synthesizing Unit <rmon_addr_gen>.
    Related source file is "src/mac_src/rmon/rmon_addr_gen.v".
    Found finite state machine <FSM_6> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | ClkEna                    (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Reg_drop_apply>.
    Found 5-bit register for signal <Reg_addr>.
    Found 1-bit register for signal <Apply_rmon_dl1>.
    Found 1-bit register for signal <Apply_rmon_dl2>.
    Found 3-bit register for signal <Pkt_err_type_rmon_dl1>.
    Found 16-bit register for signal <Pkt_length_rmon_dl1>.
    Found 3-bit register for signal <Pkt_type_rmon_dl1>.
    Found 3-bit register for signal <PktErrTypeReg>.
    Found 16-bit register for signal <PktLengthReg>.
    Found 3-bit register for signal <PktTypeReg>.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0000> created at line 174.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0001> created at line 178.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0002> created at line 180.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0003> created at line 182.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0004> created at line 184.
    Found 16-bit comparator less for signal <Reg_addr$cmp_lt0005> created at line 186.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  52 D-type flip-flop(s).
	inferred   6 Comparator(s).
Unit <rmon_addr_gen> synthesized.


Synthesizing Unit <rmon_ctrl>.
    Related source file is "src/mac_src/rmon/rmon_ctrl.v".
    Found finite state machine <FSM_7> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 10                                             |
    | Inputs             | 6                                              |
    | Outputs            | 9                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Clock enable       | ClkEna                    (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0001                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <CurrentState_reg>.
    Found 32-bit register for signal <CPU_rd_dout>.
    Found 32-bit register for signal <Dina>.
    Found 1-bit register for signal <CPU_rd_apply_dl1>.
    Found 1-bit register for signal <CPU_rd_apply_dl2>.
    Found 1-bit register for signal <CPU_rd_apply_reg>.
    Found 3-bit register for signal <CurrentState_reg>.
    Found 32-bit adder for signal <Dina$addsub0000>.
    Found 5-bit up counter for signal <StepCounter>.
    Found 3-bit comparator equal for signal <StepCounter$cmp_eq0001> created at line 97.
    Found 3-bit comparator not equal for signal <StepCounter$cmp_ne0000> created at line 97.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  67 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <rmon_ctrl> synthesized.


Synthesizing Unit <M8_1E>.
    Related source file is "src/other_src/M8_1E.v".
Unit <M8_1E> synthesized.


Synthesizing Unit <sram_addr_count>.
    Related source file is "src/mac_buf_src/sram_addr_count.v".
WARNING:Xst:647 - Input <Number> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_8> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | State$and0000             (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 17-bit register for signal <AddrCalc>.
    Found 17-bit adder for signal <$add0000> created at line 45.
    Found 17-bit comparator less for signal <AddrCalcComp>.
    Found 17-bit register for signal <AddrStart>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  34 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <sram_addr_count> synthesized.


Synthesizing Unit <tx_buffer_fsm_new>.
    Related source file is "src/_temp_src/tx_buffer_fsm_new.v".
    Found 12-bit comparator less for signal <WriteEna>.
    Found 8-bit comparator greater for signal <ReadEna>.
    Found 8-bit updown counter for signal <PacketCount>.
    Found 1-bit register for signal <WriteEndx>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <tx_buffer_fsm_new> synthesized.


Synthesizing Unit <tx_write_fsm>.
    Related source file is "src/_temp_src/tx_write_fsm.v".
    Found finite state machine <FSM_9> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 36-bit register for signal <WriteData>.
    Found 1-bit register for signal <BufTxRd>.
    Found 1-bit register for signal <WriteEna>.
    Found 1-bit register for signal <WriteEnd>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  39 D-type flip-flop(s).
Unit <tx_write_fsm> synthesized.


Synthesizing Unit <tx_read_fsm>.
    Related source file is "src/_temp_src/tx_read_fsm.v".
WARNING:Xst:647 - Input <ReadData<34>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_10> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | State$not0000             (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <MacTxData>.
    Found 2-bit register for signal <MacTxBe>.
    Found 1-bit register for signal <MacTxSop>.
    Found 1-bit register for signal <MacTxEop>.
    Found 1-bit register for signal <ReadEnd>.
    Found 1-bit register for signal <MacTxWr>.
    Found 1-bit register for signal <MacTxSopx>.
    Found 1-bit register for signal <ReadEnaInt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  40 D-type flip-flop(s).
Unit <tx_read_fsm> synthesized.


Synthesizing Unit <port_regs_2>.
    Related source file is "src/mac_buf_src/port_regs.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <PortAcceptFrameType>.
    Found 3-bit register for signal <MacSrcFilterNum>.
    Found 3-bit register for signal <MacDstFilterNum>.
    Found 3-bit register for signal <PortPriority>.
    Found 24-bit register for signal <PortTrafficClassMap>.
    Found 1-bit register for signal <MacReset>.
    Found 24-bit register for signal <PortIngressPriorityMap>.
    Found 3-bit register for signal <PortState>.
    Found 1-bit register for signal <MacSrcFilterEna>.
    Found 1-bit register for signal <MacDstFilterEna>.
    Found 4-bit register for signal <PortNumber>.
    Found 48-bit register for signal <MacDst0Filter>.
    Found 48-bit register for signal <MacDst0FilterMask>.
    Found 48-bit register for signal <MacDst1Filter>.
    Found 48-bit register for signal <MacDst1FilterMask>.
    Found 48-bit register for signal <MacDst2Filter>.
    Found 48-bit register for signal <MacDst2FilterMask>.
    Found 48-bit register for signal <MacDst3Filter>.
    Found 48-bit register for signal <MacDst3FilterMask>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/1/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/2/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/3/MacMux>.
    Found 4-bit comparator less for signal <MacReset$cmp_lt0000> created at line 280.
    Found 4-bit up counter for signal <MacResetCount>.
    Found 4-bit comparator greatequal for signal <MacResetCount$cmp_ge0000> created at line 280.
    Found 48-bit register for signal <MacSrc0Filter>.
    Found 48-bit register for signal <MacSrc1Filter>.
    Found 48-bit register for signal <MacSrc2Filter>.
    Found 48-bit register for signal <MacSrc3Filter>.
    Found 48-bit register for signal <MacSrc4Filter>.
    Found 48-bit register for signal <MacSrc5Filter>.
    Found 48-bit register for signal <MacSrc6Filter>.
    Found 48-bit register for signal <MacSrc7Filter>.
    Summary:
	inferred   1 Counter(s).
	inferred 829 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 144 Multiplexer(s).
Unit <port_regs_2> synthesized.


Synthesizing Unit <port_regs_3>.
    Related source file is "src/mac_buf_src/port_regs.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <PortAcceptFrameType>.
    Found 3-bit register for signal <MacSrcFilterNum>.
    Found 3-bit register for signal <MacDstFilterNum>.
    Found 3-bit register for signal <PortPriority>.
    Found 24-bit register for signal <PortTrafficClassMap>.
    Found 1-bit register for signal <MacReset>.
    Found 24-bit register for signal <PortIngressPriorityMap>.
    Found 3-bit register for signal <PortState>.
    Found 1-bit register for signal <MacSrcFilterEna>.
    Found 1-bit register for signal <MacDstFilterEna>.
    Found 4-bit register for signal <PortNumber>.
    Found 48-bit register for signal <MacDst0Filter>.
    Found 48-bit register for signal <MacDst0FilterMask>.
    Found 48-bit register for signal <MacDst1Filter>.
    Found 48-bit register for signal <MacDst1FilterMask>.
    Found 48-bit register for signal <MacDst2Filter>.
    Found 48-bit register for signal <MacDst2FilterMask>.
    Found 48-bit register for signal <MacDst3Filter>.
    Found 48-bit register for signal <MacDst3FilterMask>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/1/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/2/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/3/MacMux>.
    Found 4-bit comparator less for signal <MacReset$cmp_lt0000> created at line 280.
    Found 4-bit up counter for signal <MacResetCount>.
    Found 4-bit comparator greatequal for signal <MacResetCount$cmp_ge0000> created at line 280.
    Found 48-bit register for signal <MacSrc0Filter>.
    Found 48-bit register for signal <MacSrc1Filter>.
    Found 48-bit register for signal <MacSrc2Filter>.
    Found 48-bit register for signal <MacSrc3Filter>.
    Found 48-bit register for signal <MacSrc4Filter>.
    Found 48-bit register for signal <MacSrc5Filter>.
    Found 48-bit register for signal <MacSrc6Filter>.
    Found 48-bit register for signal <MacSrc7Filter>.
    Summary:
	inferred   1 Counter(s).
	inferred 829 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 144 Multiplexer(s).
Unit <port_regs_3> synthesized.


Synthesizing Unit <port_regs_4>.
    Related source file is "src/mac_buf_src/port_regs.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <PortAcceptFrameType>.
    Found 3-bit register for signal <MacSrcFilterNum>.
    Found 3-bit register for signal <MacDstFilterNum>.
    Found 3-bit register for signal <PortPriority>.
    Found 24-bit register for signal <PortTrafficClassMap>.
    Found 1-bit register for signal <MacReset>.
    Found 24-bit register for signal <PortIngressPriorityMap>.
    Found 3-bit register for signal <PortState>.
    Found 1-bit register for signal <MacSrcFilterEna>.
    Found 1-bit register for signal <MacDstFilterEna>.
    Found 4-bit register for signal <PortNumber>.
    Found 48-bit register for signal <MacDst0Filter>.
    Found 48-bit register for signal <MacDst0FilterMask>.
    Found 48-bit register for signal <MacDst1Filter>.
    Found 48-bit register for signal <MacDst1FilterMask>.
    Found 48-bit register for signal <MacDst2Filter>.
    Found 48-bit register for signal <MacDst2FilterMask>.
    Found 48-bit register for signal <MacDst3Filter>.
    Found 48-bit register for signal <MacDst3FilterMask>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/1/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/2/MacMux>.
    Found 48-bit 8-to-1 multiplexer for signal <MacMux/3/MacMux>.
    Found 4-bit comparator less for signal <MacReset$cmp_lt0000> created at line 280.
    Found 4-bit up counter for signal <MacResetCount>.
    Found 4-bit comparator greatequal for signal <MacResetCount$cmp_ge0000> created at line 280.
    Found 48-bit register for signal <MacSrc0Filter>.
    Found 48-bit register for signal <MacSrc1Filter>.
    Found 48-bit register for signal <MacSrc2Filter>.
    Found 48-bit register for signal <MacSrc3Filter>.
    Found 48-bit register for signal <MacSrc4Filter>.
    Found 48-bit register for signal <MacSrc5Filter>.
    Found 48-bit register for signal <MacSrc6Filter>.
    Found 48-bit register for signal <MacSrc7Filter>.
    Summary:
	inferred   1 Counter(s).
	inferred 829 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 144 Multiplexer(s).
Unit <port_regs_4> synthesized.


Synthesizing Unit <select_source>.
    Related source file is "src/bus_src/select_source.v".
WARNING:Xst:647 - Input <Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit 4-to-1 multiplexer for signal <MuxChannel/1/MuxChannel>.
    Found 3-bit 4-to-1 multiplexer for signal <MuxChannel/2/MuxChannel>.
    Found 3-bit 4-to-1 multiplexer for signal <MuxChannel/3/MuxChannel>.
    Found 3-bit 4-to-1 multiplexer for signal <MuxChannel/4/MuxChannel>.
    Found 2-bit 4-to-1 multiplexer for signal <MuxChannelNumber/1/MuxChannelNumber>.
    Found 2-bit 4-to-1 multiplexer for signal <MuxPriority/1/MuxPriority>.
    Summary:
	inferred  16 Multiplexer(s).
Unit <select_source> synthesized.


Synthesizing Unit <priority_packet_counter>.
    Related source file is "src/bus_src/priority_packet_counter.v".
    Found 16-bit updown counter for signal <Counter>.
    Found 16-bit comparator greater for signal <Full$cmp_gt0000> created at line 32.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <priority_packet_counter> synthesized.


Synthesizing Unit <priority_rd_addr_counter>.
    Related source file is "src/bus_src/priority_rd_addr_counter.v".
WARNING:Xst:647 - Input <AddrMax> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 17-bit register for signal <Addr>.
    Summary:
	inferred  17 D-type flip-flop(s).
Unit <priority_rd_addr_counter> synthesized.


Synthesizing Unit <pci_to_mac_fsm>.
    Related source file is "src/_temp_src/pci_to_mac_fsm.v".
WARNING:Xst:647 - Input <LvdsTxData<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <LvdsTxPa> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <LvdsTxSop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_11> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <Ena>.
    Found 2-bit register for signal <Sel>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 D-type flip-flop(s).
Unit <pci_to_mac_fsm> synthesized.


Synthesizing Unit <sram_write_mux>.
    Related source file is "src/arbiter_src/sram_write_mux.v".
WARNING:Xst:647 - Input <Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 72-bit register for signal <UserWriteData>.
    Found 20-bit register for signal <UserWriteAddr>.
    Found 1-bit register for signal <UserWrite>.
    Summary:
	inferred  93 D-type flip-flop(s).
Unit <sram_write_mux> synthesized.


Synthesizing Unit <sram_read_mux>.
    Related source file is "src/arbiter_src/sram_read_mux.v".
WARNING:Xst:647 - Input <Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 20-bit register for signal <UserReadAddr>.
    Found 1-bit register for signal <UserRead>.
    Found 3-bit comparator greatequal for signal <Ch5ReadData$cmp_ge0000> created at line 122.
    Found 1-bit register for signal <SramAccessReg>.
    Found 1-bit register for signal <SramAccessRegReg>.
    Found 2-bit register for signal <SramAccessSelReg>.
    Found 2-bit register for signal <SramAccessSelRegReg>.
    Summary:
	inferred  27 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <sram_read_mux> synthesized.


Synthesizing Unit <mdio_fsm>.
    Related source file is "src/other_src/mdio_fsm.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <State> of Case statement line 55 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <State> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_12> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 17                                             |
    | Inputs             | 5                                              |
    | Outputs            | 9                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | ClockEna                  (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <SdaOut>.
    Found 1-bit register for signal <Dir>.
    Found 1-bit register for signal <Busy>.
    Found 16-bit register for signal <DataReceive>.
    Found 4-bit register for signal <ByteCount>.
    Found 4-bit comparator less for signal <ByteCount$cmp_lt0000> created at line 71.
    Found 4-bit comparator less for signal <ByteCount$cmp_lt0001> created at line 88.
    Found 4-bit comparator less for signal <ByteCount$cmp_lt0002> created at line 132.
    Found 4-bit adder for signal <ByteCount$share0000> created at line 55.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <mdio_fsm> synthesized.


Synthesizing Unit <iic_state_machine>.
    Related source file is "src/other_src/iic_state_machine fsm.v".
WARNING:Xst:647 - Input <SclIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SlaveAddr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_13> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 27                                             |
    | Inputs             | 8                                              |
    | Outputs            | 10                                             |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | State$and0000             (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <SdaOut>.
    Found 1-bit register for signal <Dir>.
    Found 1-bit register for signal <Busy>.
    Found 8-bit register for signal <DataReceive>.
    Found 1-bit register for signal <Error>.
    Found 1-bit register for signal <SclOut>.
    Found 1-bit register for signal <AddrTransmitFlag>.
    Found 2-bit register for signal <BitCount>.
    Found 2-bit adder for signal <BitCount$addsub0000>.
    Found 2-bit comparator less for signal <BitCount$cmp_lt0000> created at line 122.
    Found 3-bit register for signal <ByteCount>.
    Found 3-bit adder for signal <ByteCount$addsub0000>.
    Found 1-bit register for signal <DataTransmitFlag>.
    Found 12-bit up counter for signal <IicClockCount>.
    Found 1-bit register for signal <IicClockEna>.
    Found 1-bit register for signal <SecondStartFlag>.
    Found 3-bit comparator less for signal <State$cmp_lt0000> created at line 147.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <iic_state_machine> synthesized.


Synthesizing Unit <one_sfp_irq>.
    Related source file is "src/other_src/one_sfp_irq.v".
    Found 1-bit register for signal <PresentReg>.
    Found 1-bit register for signal <PresentRegReg>.
    Found 1-bit xor2 for signal <PresentStrobe>.
    Found 1-bit register for signal <TempIrq>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <one_sfp_irq> synthesized.


Synthesizing Unit <one_sfp_als>.
    Related source file is "src/other_src/one_sfp_als.v".
    Found finite state machine <FSM_14> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 5                                              |
    | Outputs            | 4                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | State$not0000             (positive)           |
    | Reset              | Rst                       (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <Counter>.
    Found 8-bit adder for signal <Counter$share0000> created at line 51.
    Found 8-bit up counter for signal <Counter2>.
    Found 1-bit register for signal <TxDisableInt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <one_sfp_als> synthesized.


Synthesizing Unit <reset_gen>.
    Related source file is "src/other_src/reset_gen.v".
    Found 1-bit register for signal <Reset>.
    Found 24-bit up counter for signal <Count>.
    Found 24-bit comparator greatequal for signal <Count$cmp_ge0000> created at line 27.
    Found 1-bit register for signal <State>.
    Found 24-bit comparator less for signal <State$cmp_lt0000> created at line 27.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <reset_gen> synthesized.


Synthesizing Unit <mac_mux>.
    Related source file is "src/_temp_src/mac_mux.v".
    Found 1-bit 4-to-1 multiplexer for signal <MuxBit/1/MuxBit>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <mac_mux> synthesized.


Synthesizing Unit <memory_arbiter>.
    Related source file is "src/arbiter_src/memory_arbiter.v".
Unit <memory_arbiter> synthesized.


Synthesizing Unit <mdio>.
    Related source file is "src/other_src/mdio.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SysDin<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <MdioSel>.
    Found 7-bit up counter for signal <CountMdioClock>.
    Found 1-bit register for signal <MdioClock>.
    Found 1-bit register for signal <MdioClockEnaTemp>.
    Found 16-bit register for signal <MdioDataWrite>.
    Found 2-bit register for signal <MdioOpcode>.
    Found 5-bit register for signal <MdioPhyAddr>.
    Found 5-bit register for signal <MdioRegAddr>.
    Found 1-bit register for signal <MdioStart>.
    Summary:
	inferred   1 Counter(s).
	inferred  31 D-type flip-flop(s).
Unit <mdio> synthesized.


Synthesizing Unit <phy_new>.
    Related source file is "src/other_src/phy_new.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ClockEna> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <Phy0Config1Sel>.
    Found 4-bit register for signal <Phy0Config2Sel>.
    Found 4-bit register for signal <Phy0Config3Sel>.
    Found 4-bit register for signal <Phy0Config4Sel>.
    Found 4-bit register for signal <Phy1Config1Sel>.
    Found 4-bit register for signal <Phy1Config2Sel>.
    Found 4-bit register for signal <Phy1Config3Sel>.
    Found 4-bit register for signal <Phy1Config4Sel>.
    Found 4-bit register for signal <Phy2Config1Sel>.
    Found 4-bit register for signal <Phy2Config2Sel>.
    Found 4-bit register for signal <Phy2Config3Sel>.
    Found 4-bit register for signal <Phy2Config4Sel>.
    Found 4-bit register for signal <Phy3Config1Sel>.
    Found 4-bit register for signal <Phy3Config2Sel>.
    Found 4-bit register for signal <Phy3Config3Sel>.
    Found 4-bit register for signal <Phy3Config4Sel>.
    Found 4-bit register for signal <PhyConfig0Sel>.
    Found 4-bit register for signal <PhyConfig1Sel>.
    Summary:
	inferred  36 D-type flip-flop(s).
Unit <phy_new> synthesized.


Synthesizing Unit <input_dcm>.
    Related source file is "input_dcm.v".
Unit <input_dcm> synthesized.


Synthesizing Unit <sram_write_clock>.
    Related source file is "src/sram_src/sram_write_clock.v".
Unit <sram_write_clock> synthesized.


Synthesizing Unit <tx_buffer_new>.
    Related source file is "src/_temp_src/tx_buffer_new.v".
Unit <tx_buffer_new> synthesized.


Synthesizing Unit <regs_int>.
    Related source file is "src/mac_src/regs_int.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ClockEna> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SysDin<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <RX_APPEND_CRC>.
    Found 1-bit register for signal <MAC_tx_add_en>.
    Found 1-bit register for signal <MAC_rx_add_chk_en>.
    Found 6-bit register for signal <RX_IFG_SET>.
    Found 16-bit register for signal <RX_MAX_LENGTH>.
    Found 5-bit register for signal <Tx_Hwmark>.
    Found 1-bit register for signal <CRC_chk_en>.
    Found 5-bit register for signal <Rx_Hwmark>.
    Found 3-bit register for signal <MAC_tx_add_prom_add>.
    Found 1-bit register for signal <xoff_cpu>.
    Found 6-bit register for signal <CPU_rd_addr>.
    Found 1-bit register for signal <CPU_rd_apply>.
    Found 3-bit register for signal <MAC_rx_add_prom_add>.
    Found 1-bit register for signal <tx_pause_en>.
    Found 1-bit register for signal <pause_frame_send_en>.
    Found 1-bit register for signal <Line_loop_en>.
    Found 1-bit register for signal <FullDuplex>.
    Found 8-bit register for signal <MAC_rx_add_prom_data>.
    Found 8-bit register for signal <MAC_tx_add_prom_data>.
    Found 6-bit register for signal <IFGset>.
    Found 1-bit register for signal <MAC_tx_add_prom_wr>.
    Found 3-bit register for signal <Speed>.
    Found 1-bit register for signal <broadcast_filter_en>.
    Found 1-bit register for signal <xon_cpu>.
    Found 7-bit register for signal <RX_MIN_LENGTH>.
    Found 16-bit register for signal <broadcast_bucket_depth>.
    Found 5-bit register for signal <Tx_Lwmark>.
    Found 1-bit register for signal <MAC_rx_add_prom_wr>.
    Found 4-bit register for signal <MaxRetry>.
    Found 16-bit register for signal <pause_quanta_set>.
    Found 16-bit register for signal <broadcast_bucket_interval>.
    Found 5-bit register for signal <Rx_Lwmark>.
    Found 32-bit register for signal <RmonDout>.
    Found 1-bit register for signal <State>.
    Summary:
	inferred 123 D-type flip-flop(s).
Unit <regs_int> synthesized.


Synthesizing Unit <clock_ctrl_new>.
    Related source file is "src/mac_src/clock_ctrl_new.v".
WARNING:Xst:647 - Input <Speed<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <PhyCE>.
    Found 1-bit register for signal <MacTxClockEna>.
    Found 1-bit register for signal <TxClockDiv>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock_ctrl_new> synthesized.


Synthesizing Unit <mac_rx_ff_new>.
    Related source file is "src/mac_src/mac_rx/mac_rx_ff_new.v".
    Found 1-bit register for signal <Packet_number_add_dl1>.
    Found 1-bit register for signal <Packet_number_add_dl2>.
    Found 1-bit register for signal <Packet_number_add_reg>.
    Found 1-bit xor2 for signal <Packet_number_add_user>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <mac_rx_ff_new> synthesized.


Synthesizing Unit <mac_rx_add_chk>.
    Related source file is "src/mac_src/mac_rx/mac_rx_add_chk.v".
    Found 1-bit register for signal <MAC_rx_add_chk_err>.
    Found 3-bit up counter for signal <addr_rd>.
    Found 8-bit register for signal <data_dl1>.
    Found 1-bit register for signal <MAC_add_en_dl1>.
    Found 1-bit register for signal <MAC_add_prom_wr_dl1>.
    Found 1-bit register for signal <MAC_add_prom_wr_dl2>.
    Found 8-bit comparator equal for signal <MAC_rx_add_chk_err$cmp_eq0000> created at line 84.
    Summary:
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <mac_rx_add_chk> synthesized.


Synthesizing Unit <mac_tx_addr_add>.
    Related source file is "src/mac_src/mac_tx/mac_tx_addr_add.v".
WARNING:Xst:653 - Signal <addr_wr> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <addr_rd> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <add_wr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 3-bit up counter for signal <add_rd>.
    Found 1-bit register for signal <MAC_add_prom_wr_dl1>.
    Found 1-bit register for signal <MAC_add_prom_wr_dl2>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <mac_tx_addr_add> synthesized.


Synthesizing Unit <mac_tx_ff>.
    Related source file is "src/mac_src/mac_tx/mac_tx_ff.v".
WARNING:Xst:646 - Signal <Tx_mac_sop_dl1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Tx_mac_eop_dl1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Fifo_rd_dl1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Add_wr_gray_tmp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Add_rd_reg_dl1<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Add_rd_pluse> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Add_rd_gray_tmp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_15> for signal <Current_state_SYS>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk_SYS                   (rising_edge)        |
    | Clock enable       | Clk_SYS_ena               (positive)           |
    | Reset              | Reset                     (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <Current_state_MAC>.
    Using one-hot encoding for signal <Next_state_MAC>.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <Current_state_MAC> of Case statement line 428 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <Current_state_MAC> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <Current_state_MAC_reg>.
    Found 1-bit register for signal <Fifo_data_err_empty>.
    Found 1-bit register for signal <Tx_mac_wa>.
    Found 1-bit register for signal <Fifo_da>.
    Found 1-bit register for signal <Fifo_ra>.
    Found 9-bit up counter for signal <Add_rd>.
    Found 9-bit register for signal <Add_rd_gray>.
    Found 1-bit xor2 for signal <Add_rd_gray_0$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_1$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_2$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_3$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_4$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_5$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_6$xor0000> created at line 500.
    Found 1-bit xor2 for signal <Add_rd_gray_7$xor0000> created at line 500.
    Found 9-bit register for signal <Add_rd_gray_dl1>.
    Found 1-bit register for signal <Add_rd_jump>.
    Found 1-bit register for signal <Add_rd_jump_tmp>.
    Found 1-bit register for signal <Add_rd_jump_tmp_pl1>.
    Found 1-bit register for signal <Add_rd_jump_wr_pl1>.
    Found 9-bit register for signal <Add_rd_reg>.
    Found 9-bit register for signal <Add_rd_reg_dl1>.
    Found 1-bit register for signal <Add_rd_reg_rdy>.
    Found 1-bit register for signal <Add_rd_reg_rdy_dl1>.
    Found 1-bit register for signal <Add_rd_reg_rdy_dl2>.
    Found 1-bit register for signal <Add_rd_reg_rdy_tmp>.
    Found 9-bit register for signal <Add_rd_ungray>.
    Found 1-bit xor2 for signal <Add_rd_ungray_0$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_0$xor0001> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_1$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_2$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_3$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_4$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_5$xor0000> created at line 253.
    Found 1-bit xor2 for signal <Add_rd_ungray_6$xor0000> created at line 253.
    Found 9-bit up counter for signal <Add_wr>.
    Found 9-bit register for signal <Add_wr_gray>.
    Found 1-bit xor2 for signal <Add_wr_gray_0$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_1$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_2$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_3$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_4$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_5$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_6$xor0000> created at line 230.
    Found 1-bit xor2 for signal <Add_wr_gray_7$xor0000> created at line 230.
    Found 9-bit register for signal <Add_wr_gray_dl1>.
    Found 9-bit adder for signal <Add_wr_pluse>.
    Found 9-bit adder for signal <Add_wr_pluse_pluse>.
    Found 9-bit register for signal <Add_wr_ungray>.
    Found 1-bit xor2 for signal <Add_wr_ungray_0$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_0$xor0001> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_1$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_2$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_3$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_4$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_5$xor0000> created at line 515.
    Found 1-bit xor2 for signal <Add_wr_ungray_6$xor0000> created at line 515.
    Found 1-bit register for signal <AlmostFull>.
    Found 9-bit comparator equal for signal <AlmostFull$cmp_eq0000> created at line 270.
    Found 10-bit register for signal <Current_state_MAC>.
    Found 10-bit register for signal <Current_state_MAC_reg>.
    Found 36-bit register for signal <Dout_dl1>.
    Found 36-bit register for signal <Dout_reg>.
    Found 1-bit register for signal <Empty>.
    Found 9-bit comparator equal for signal <Empty$cmp_eq0000> created at line 523.
    Found 5-bit register for signal <Fifo_data_count>.
    Found 5-bit subtractor for signal <Fifo_data_count$mux0000>.
    Found 1-bit register for signal <Fifo_ra_tmp>.
    Found 6-bit comparator greatequal for signal <Fifo_ra_tmp$cmp_ge0000> created at line 364.
    Found 5-bit comparator greatequal for signal <Fifo_ra_tmp$cmp_ge0001> created at line 364.
    Found 9-bit comparator equal for signal <Full$cmp_eq0000> created at line 261.
    Found 1-bit register for signal <Packet_number_add>.
    Found 6-bit updown counter for signal <Packet_number_inFF>.
    Found 6-bit register for signal <Packet_number_inFF_reg>.
    Found 1-bit register for signal <Packet_number_sub_dl1>.
    Found 1-bit register for signal <Packet_number_sub_dl2>.
    Found 1-bit register for signal <Packet_number_sub_edge>.
    Found 1-bit register for signal <Pkt_sub_apply>.
    Found 1-bit register for signal <Pkt_sub_apply_tmp>.
    Found 5-bit register for signal <Tx_Hwmark_pl>.
    Found 5-bit register for signal <Tx_Lwmark_pl>.
    Found 2-bit register for signal <Tx_mac_BE_dl1>.
    Found 32-bit register for signal <Tx_mac_data_dl1>.
    Found 5-bit comparator greatequal for signal <Tx_mac_wa$cmp_ge0000> created at line 386.
    Found 5-bit comparator greatequal for signal <Tx_mac_wa$cmp_ge0001> created at line 384.
    Found 5-bit comparator less for signal <Tx_mac_wa$cmp_lt0000> created at line 384.
    Found 1-bit register for signal <Tx_mac_wr_dl1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred 221 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   8 Comparator(s).
Unit <mac_tx_ff> synthesized.


Synthesizing Unit <rmon_dpram>.
    Related source file is "src/mac_src/rmon/rmon_dpram.v".
WARNING:Xst:647 - Input <Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <rmon_dpram> synthesized.


Synthesizing Unit <rx_read_fsm>.
    Related source file is "src/mac_buf_src/rx_read_fsm.v".
WARNING:Xst:647 - Input <PortNumber<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <SopFlag> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_16> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 9                                              |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | ClockEna                  (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <FifoReadEna>.
    Found 1-bit register for signal <SramWriteEna>.
    Found 1-bit register for signal <End>.
    Found 1-bit register for signal <FindEop>.
    Found 17-bit 4-to-1 multiplexer for signal <MuxSramWriteAddr/1/MuxSramWriteAddr>.
    Found 36-bit register for signal <SramWriteDataA>.
    Found 36-bit register for signal <SramWriteDataB>.
    Found 9-bit comparator greater for signal <State$cmp_gt0000> created at line 73.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  76 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  17 Multiplexer(s).
Unit <rx_read_fsm> synthesized.


Synthesizing Unit <mux_priority>.
    Related source file is "src/mac_buf_src/mux_priority.v".
Unit <mux_priority> synthesized.


Synthesizing Unit <one_channel_packet_counters>.
    Related source file is "src/bus_src/one_channel_packet_counters.v".
    Found 2-bit register for signal <Priority>.
    Found 1-bit register for signal <Full>.
    Found 17-bit 4-to-1 multiplexer for signal <MuxAddr/1/MuxAddr>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <one_channel_packet_counters> synthesized.


Synthesizing Unit <rx_ddr>.
    Related source file is "src/serdes_src/rx_ddr.v".
    Found 8-bit register for signal <Ctrl>.
    Found 32-bit register for signal <Data>.
    Found 4-bit register for signal <OddCtrl_FF>.
    Found 16-bit register for signal <OddData_FF>.
    Summary:
	inferred  60 D-type flip-flop(s).
Unit <rx_ddr> synthesized.


Synthesizing Unit <tx_write>.
    Related source file is "src/serdes_src/tx_write.v".
Unit <tx_write> synthesized.


Synthesizing Unit <sram_address>.
    Related source file is "src/sram_src/sram_address.v".
Unit <sram_address> synthesized.


Synthesizing Unit <sram_write>.
    Related source file is "src/sram_src/sram_write.v".
Unit <sram_write> synthesized.


Synthesizing Unit <sram_read_new>.
    Related source file is "src/sram_src/sram_read_new.v".
Unit <sram_read_new> synthesized.


Synthesizing Unit <sram_read_dcm>.
    Related source file is "sram_read_dcm.v".
Unit <sram_read_dcm> synthesized.


Synthesizing Unit <sfp_irq>.
    Related source file is "src/other_src/sfp_irq.v".
Unit <sfp_irq> synthesized.


Synthesizing Unit <sfp_als>.
    Related source file is "src/other_src/sfp_als.v".
    Found 16-bit up counter for signal <LocalDiv>.
    Summary:
	inferred   1 Counter(s).
Unit <sfp_als> synthesized.


Synthesizing Unit <clock_gen>.
    Related source file is "src/other_src/clock_gen.v".
    Found 1-bit xor2 for signal <Clock1>.
    Found 1-bit register for signal <SramAccess>.
    Found 1-bit register for signal <Clock500k>.
    Found 7-bit comparator less for signal <Clock500k$cmp_lt0000> created at line 100.
    Found 1-bit register for signal <Clock500kReg>.
    Found 1-bit register for signal <Clock500kRegReg>.
    Found 2-bit up counter for signal <ClockEnaCount>.
    Found 2-bit comparator less for signal <ClockEnaCount$cmp_lt0000> created at line 78.
    Found 4-bit up counter for signal <CountDcmReset>.
    Found 4-bit comparator less for signal <CountDcmReset$cmp_lt0000> created at line 48.
    Found 1-bit register for signal <DcmReset>.
    Found 7-bit up counter for signal <TimerCount>.
    Summary:
	inferred   3 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <clock_gen> synthesized.


Synthesizing Unit <sfp>.
    Related source file is "src/other_src/sfp.v".
WARNING:Xst:647 - Input <SysRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <Sfp3RateSel>.
    Found 1-bit register for signal <Sfp2RateSel>.
    Found 1-bit register for signal <Sfp1RateSel>.
    Found 2-bit register for signal <IicSel>.
    Found 1-bit register for signal <Sfp0RateSel>.
    Found 8-bit register for signal <IicDataWriteReg>.
    Found 8-bit register for signal <IicRegAddr>.
    Found 1-bit register for signal <IicRWReg>.
    Found 8-bit register for signal <IicSlaveAddr>.
    Found 1-bit register for signal <IicStart>.
    Found 1-bit register for signal <Sfp0AlsEna>.
    Found 1-bit register for signal <Sfp0Mask>.
    Found 1-bit register for signal <Sfp0TxDisableReg>.
    Found 1-bit register for signal <Sfp1AlsEna>.
    Found 1-bit register for signal <Sfp1Mask>.
    Found 1-bit register for signal <Sfp1TxDisableReg>.
    Found 1-bit register for signal <Sfp2AlsEna>.
    Found 1-bit register for signal <Sfp2Mask>.
    Found 1-bit register for signal <Sfp2TxDisableReg>.
    Found 1-bit register for signal <Sfp3AlsEna>.
    Found 1-bit register for signal <Sfp3Mask>.
    Found 1-bit register for signal <Sfp3TxDisableReg>.
    Summary:
	inferred  44 D-type flip-flop(s).
Unit <sfp> synthesized.


Synthesizing Unit <mac_rx>.
    Related source file is "src/mac_src/mac_rx.v".
Unit <mac_rx> synthesized.


Synthesizing Unit <mac_tx>.
    Related source file is "src/mac_src/mac_tx.v".
Unit <mac_tx> synthesized.


Synthesizing Unit <rmon>.
    Related source file is "src/mac_src/rmon.v".
Unit <rmon> synthesized.


Synthesizing Unit <rx_write_fsm>.
    Related source file is "src/mac_buf_src/rx_write_fsm.v".
WARNING:Xst:646 - Signal <TrafficPriority<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_17> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 27                                             |
    | Inputs             | 13                                             |
    | Outputs            | 11                                             |
    | Clock              | Clock                     (rising_edge)        |
    | Clock enable       | ClockEna                  (positive)           |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 36-bit register for signal <FifoWriteData>.
    Found 2-bit register for signal <Priority>.
    Found 1-bit register for signal <MacRxRd>.
    Found 1-bit register for signal <Err>.
    Found 1-bit register for signal <FifoWriteEna>.
    Found 3-bit register for signal <Counter>.
    Found 3-bit comparator less for signal <Counter$cmp_lt0000> created at line 203.
    Found 3-bit comparator less for signal <Counter$cmp_lt0001> created at line 226.
    Found 3-bit adder for signal <Counter$share0000> created at line 131.
    Found 1-bit register for signal <DeleteFrame>.
    Found 3-bit register for signal <FramePriority>.
    Found 1-bit register for signal <FrameTagged>.
    Found 48-bit register for signal <MacSrc>.
    Found 48-bit comparator equal for signal <MacSrcEq>.
    Found 3-bit comparator equal for signal <State$cmp_eq0003> created at line 222.
    Found 1-bit register for signal <WriteEna>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  98 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <rx_write_fsm> synthesized.


Synthesizing Unit <rx_packet_counters>.
    Related source file is "src/bus_src/rx_packet_counters.v".
    Found 4x34-bit ROM for signal <ChannelPriority$rom0000>.
    Found 17-bit 4-to-1 multiplexer for signal <MuxAddr/1/MuxAddr>.
    Summary:
	inferred   1 ROM(s).
	inferred  17 Multiplexer(s).
Unit <rx_packet_counters> synthesized.


Synthesizing Unit <tx_ddr>.
    Related source file is "src/serdes_src/tx_ddr.v".
Unit <tx_ddr> synthesized.


Synthesizing Unit <sram_read_clock>.
    Related source file is "src/sram_src/sram_read_clock.v".
Unit <sram_read_clock> synthesized.


Synthesizing Unit <bus>.
    Related source file is "src/bus_src/bus.v".
WARNING:Xst:647 - Input <RxData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RxSop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RxPa> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RxEop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RxRa> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <ChannelSelTemp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ChannelPriorityTemp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ChannelFullTemp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ChannelAddrMin> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ChannelAddrMax> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <State> of Case statement line 140 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <State> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <StateWrite> of Case statement line 213 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <StateWrite> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_18> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 6                                              |
    | Outputs            | 5                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_19> for signal <StateWrite>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Clock                     (rising_edge)        |
    | Reset              | Reset                     (negative)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit register for signal <TxData>.
    Found 20-bit register for signal <SramReadAddr>.
    Found 1-bit register for signal <SramReadEna>.
    Found 1-bit register for signal <TxPa>.
    Found 1-bit register for signal <TxSop>.
    Found 1-bit register for signal <TxEop>.
    Found 2-bit register for signal <TxBe>.
    Found 17-bit register for signal <BusAddr>.
    Found 2-bit register for signal <BusChannelNumber>.
    Found 1-bit register for signal <BusPacketStrobe>.
    Found 2-bit register for signal <BusPriopityNumber>.
    Found 17-bit up counter for signal <ChannelAddrLoad>.
    Found 17-bit adder for signal <ChannelAddrLoad$add0000> created at line 197.
    Found 2-bit register for signal <Count>.
    Found 2-bit adder for signal <Count$share0000> created at line 140.
    Found 1-bit register for signal <FifoAReadEna>.
    Found 36-bit register for signal <FifoAWriteData>.
    Found 1-bit register for signal <FifoAWriteEna>.
    Found 1-bit register for signal <FifoBReadEna>.
    Found 36-bit register for signal <FifoBWriteData>.
    Found 1-bit register for signal <FifoBWriteEna>.
    Found 2-bit comparator greater for signal <FindPaH>.
    Found 2-bit comparator greater for signal <FindPaL>.
    Found 2-bit register for signal <Select>.
    Found 20-bit adder for signal <SramReadAddr$addsub0000> created at line 156.
    Found 2-bit comparator less for signal <State$cmp_lt0000> created at line 157.
    Found 1-bit register for signal <StateRead>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred 161 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <bus> synthesized.


Synthesizing Unit <serdes>.
    Related source file is "src/serdes_src/serdes.v".
WARNING:Xst:646 - Signal <ReceiveCtrl<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <serdes> synthesized.


Synthesizing Unit <sram_ctrl>.
    Related source file is "src/sram_src/sram_ctrl.v".
    Found 16-bit up counter for signal <CountSramOff>.
    Found 16-bit comparator less for signal <CountSramOff$cmp_lt0000> created at line 144.
    Found 1-bit register for signal <SramOffReg>.
    Found 5-bit register for signal <USER_DV_Shift>.
    Summary:
	inferred   1 Counter(s).
	inferred   6 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <sram_ctrl> synthesized.


Synthesizing Unit <mac_top_new>.
    Related source file is "src/mac_src/mac_top_new.v".
WARNING:Xst:1780 - Signal <broadcast_MAX> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <WCtrlDataStart> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <WCtrlData> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <UpdateMIIRX_DATAReg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ScanStat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Rgad> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <RStatStart> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <RStat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Prsd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Nvalid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <NoPre> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <LinkFail> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Fiad> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Divider> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CtrlData> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <mac_top_new> synthesized.


Synthesizing Unit <rx_buffer_new>.
    Related source file is "src/mac_buf_src/rx_buffer_new.v".
WARNING:Xst:647 - Input <BusPriopityNumber> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BusChannelNumber> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BusReadAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BusPacketStrobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <MacWriteAddr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FifoFull> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FifoEmpty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <rx_buffer_new> synthesized.


Synthesizing Unit <mac_and_buf_1>.
    Related source file is "src/mac_buf_src/mac_and_buf.v".
WARNING:Xst:647 - Input <SramReadData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SramReadDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <MacDstFilterNum> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterMask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterEna> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <mac_and_buf_1> synthesized.


Synthesizing Unit <mac_and_buf_2>.
    Related source file is "src/mac_buf_src/mac_and_buf.v".
WARNING:Xst:647 - Input <SramReadData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SramReadDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <MacDstFilterNum> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterMask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterEna> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <mac_and_buf_2> synthesized.


Synthesizing Unit <mac_and_buf_3>.
    Related source file is "src/mac_buf_src/mac_and_buf.v".
WARNING:Xst:647 - Input <SramReadData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SramReadDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <MacDstFilterNum> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterMask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterEna> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <mac_and_buf_3> synthesized.


Synthesizing Unit <mac_and_buf_4>.
    Related source file is "src/mac_buf_src/mac_and_buf.v".
WARNING:Xst:647 - Input <SramReadData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SramReadDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <MacDstFilterNum> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterMask> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilterEna> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MacDstFilter> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <mac_and_buf_4> synthesized.


Synthesizing Unit <top>.
    Related source file is "src/top.v".
WARNING:Xst:647 - Input <PhyClock125> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <SwithRxSop> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <SwithRxRd> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <SwithRxRa> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <SwithRxPa> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <SwithRxEop> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <SwithRxData> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:1780 - Signal <SwithRxBe> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MdioSel> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <IiicSdaOut> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <IiicDir> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <IicSclIn> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <Clock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
    Found 1-bit tristate buffer for signal <PhyMdio>.
    Found 1-bit tristate buffer for signal <Sfp0Scl>.
    Found 1-bit tristate buffer for signal <Sfp0Sda>.
    Found 1-bit tristate buffer for signal <Sfp1Scl>.
    Found 1-bit tristate buffer for signal <Sfp1Sda>.
    Found 1-bit tristate buffer for signal <Sfp2Scl>.
    Found 1-bit tristate buffer for signal <Sfp2Sda>.
    Found 1-bit tristate buffer for signal <Sfp3Scl>.
    Found 1-bit tristate buffer for signal <Sfp3Sda>.
    Found 8-bit tristate buffer for signal <Test>.
    Found 1-bit 4-to-1 multiplexer for signal <MuxIicSdaIn/1/MuxIicSdaIn>.
    Summary:
	inferred   1 Multiplexer(s).
	inferred  17 Tristate(s).
Unit <top> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x34-bit ROM                                          : 1
# Adders/Subtractors                                   : 80
 16-bit subtractor                                     : 4
 17-bit adder                                          : 17
 2-bit adder                                           : 2
 20-bit adder                                          : 1
 3-bit adder                                           : 5
 32-bit adder                                          : 5
 4-bit adder                                           : 1
 5-bit adder                                           : 1
 5-bit subtractor                                      : 8
 8-bit adder                                           : 4
 8-bit subtractor                                      : 8
 9-bit adder                                           : 24
# Counters                                             : 131
 10-bit down counter                                   : 4
 12-bit up counter                                     : 1
 16-bit down counter                                   : 4
 16-bit up counter                                     : 18
 16-bit updown counter                                 : 16
 17-bit up counter                                     : 1
 2-bit up counter                                      : 1
 24-bit up counter                                     : 2
 3-bit up counter                                      : 4
 32-bit up counter                                     : 1
 4-bit up counter                                      : 13
 5-bit up counter                                      : 8
 6-bit up counter                                      : 8
 6-bit updown counter                                  : 8
 7-bit up counter                                      : 2
 8-bit up counter                                      : 20
 8-bit updown counter                                  : 4
 9-bit up counter                                      : 16
# Registers                                            : 5732
 1-bit register                                        : 5270
 10-bit register                                       : 12
 16-bit register                                       : 45
 17-bit register                                       : 17
 2-bit register                                        : 32
 20-bit register                                       : 3
 3-bit register                                        : 89
 32-bit register                                       : 36
 36-bit register                                       : 30
 4-bit register                                        : 27
 5-bit register                                        : 51
 6-bit register                                        : 16
 7-bit register                                        : 4
 72-bit register                                       : 1
 8-bit register                                        : 71
 9-bit register                                        : 28
# Comparators                                          : 280
 12-bit comparator less                                : 4
 16-bit comparator equal                               : 8
 16-bit comparator greatequal                          : 12
 16-bit comparator greater                             : 20
 16-bit comparator less                                : 53
 16-bit comparator lessequal                           : 12
 16-bit comparator not equal                           : 4
 17-bit comparator less                                : 16
 2-bit comparator greater                              : 2
 2-bit comparator less                                 : 3
 24-bit comparator greatequal                          : 2
 24-bit comparator less                                : 2
 3-bit comparator equal                                : 8
 3-bit comparator greatequal                           : 1
 3-bit comparator less                                 : 9
 3-bit comparator not equal                            : 4
 32-bit comparator less                                : 1
 4-bit comparator greatequal                           : 4
 4-bit comparator greater                              : 4
 4-bit comparator less                                 : 8
 4-bit comparator lessequal                            : 4
 48-bit comparator equal                               : 4
 5-bit comparator greatequal                           : 12
 5-bit comparator greater                              : 4
 5-bit comparator less                                 : 10
 5-bit comparator lessequal                            : 4
 6-bit comparator greatequal                           : 4
 6-bit comparator less                                 : 4
 7-bit comparator less                                 : 1
 8-bit comparator equal                                : 12
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 4
 9-bit comparator equal                                : 32
 9-bit comparator greater                              : 4
# Multiplexers                                         : 36
 1-bit 32-to-1 multiplexer                             : 1
 1-bit 4-to-1 multiplexer                              : 2
 17-bit 4-to-1 multiplexer                             : 9
 2-bit 4-to-1 multiplexer                              : 2
 3-bit 4-to-1 multiplexer                              : 4
 32-bit 4-to-1 multiplexer                             : 5
 32-bit 8-to-1 multiplexer                             : 1
 48-bit 8-to-1 multiplexer                             : 12
# Decoders                                             : 1
 1-of-8 decoder                                        : 1
# Tristates                                            : 17
 1-bit tristate buffer                                 : 17
# Xors                                                 : 689
 1-bit xor2                                            : 473
 1-bit xor3                                            : 96
 1-bit xor4                                            : 104
 1-bit xor6                                            : 16

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_19> for best encoding.
Optimizing FSM <bus/StateWrite/FSM> on signal <StateWrite[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM <FSM_18> for best encoding.
Optimizing FSM <bus/State/FSM> on signal <State[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM <FSM_17> for best encoding.
Optimizing FSM <mac_0/rx_buf/fsm_write/State/FSM> on signal <State[1:9]> with one-hot encoding.
Optimizing FSM <mac_1/rx_buf/fsm_write/State/FSM> on signal <State[1:9]> with one-hot encoding.
Optimizing FSM <mac_2/rx_buf/fsm_write/State/FSM> on signal <State[1:9]> with one-hot encoding.
Optimizing FSM <mac_3/rx_buf/fsm_write/State/FSM> on signal <State[1:9]> with one-hot encoding.
--------------------
 State | Encoding
--------------------
 0000  | 000000001
 0001  | 000000010
 0010  | 000000100
 0011  | 000001000
 0100  | 000010000
 0101  | 001000000
 0110  | 000100000
 0111  | 010000000
 1000  | 100000000
--------------------
Analyzing FSM <FSM_16> for best encoding.
Optimizing FSM <mac_0/rx_buf/fsm_read/State/FSM> on signal <State[1:3]> with user encoding.
Optimizing FSM <mac_1/rx_buf/fsm_read/State/FSM> on signal <State[1:3]> with user encoding.
Optimizing FSM <mac_2/rx_buf/fsm_read/State/FSM> on signal <State[1:3]> with user encoding.
Optimizing FSM <mac_3/rx_buf/fsm_read/State/FSM> on signal <State[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
-------------------
Analyzing FSM <FSM_15> for best encoding.
Optimizing FSM <mac_0/mac/mac_tx/mac_tx_ff/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with gray encoding.
Optimizing FSM <mac_1/mac/mac_tx/mac_tx_ff/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with gray encoding.
Optimizing FSM <mac_2/mac/mac_tx/mac_tx_ff/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with gray encoding.
Optimizing FSM <mac_3/mac/mac_tx/mac_tx_ff/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0000  | 000
 0010  | 001
 0011  | 011
 0100  | 010
 0101  | 111
 0111  | 101
 1000  | 110
-------------------
Analyzing FSM <FSM_14> for best encoding.
Optimizing FSM <sfp/als/als_sfp0/State/FSM> on signal <State[1:2]> with gray encoding.
Optimizing FSM <sfp/als/als_sfp1/State/FSM> on signal <State[1:2]> with gray encoding.
Optimizing FSM <sfp/als/als_sfp2/State/FSM> on signal <State[1:2]> with gray encoding.
Optimizing FSM <sfp/als/als_sfp3/State/FSM> on signal <State[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 00
 001   | 01
 010   | 11
 011   | 10
-------------------
Analyzing FSM <FSM_13> for best encoding.
Optimizing FSM <sfp/fsm/State/FSM> on signal <State[1:9]> with one-hot encoding.
--------------------
 State | Encoding
--------------------
 0000  | 000000001
 0001  | 000000010
 0010  | 000000100
 0011  | 000001000
 0100  | 100000000
 0101  | 000100000
 0110  | 010000000
 0111  | 001000000
 1000  | 000010000
--------------------
Analyzing FSM <FSM_12> for best encoding.
Optimizing FSM <mdio/fsm/State/FSM> on signal <State[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 011
 011   | 010
 100   | 110
 101   | 111
 110   | 101
 111   | 100
-------------------
Analyzing FSM <FSM_11> for best encoding.
Optimizing FSM <mac_mux/fsm/State/FSM> on signal <State[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
-------------------
Analyzing FSM <FSM_10> for best encoding.
Optimizing FSM <mac_0/tx_buf/fsm_read/State/FSM> on signal <State[1:7]> with one-hot encoding.
Optimizing FSM <mac_1/tx_buf/fsm_read/State/FSM> on signal <State[1:7]> with one-hot encoding.
Optimizing FSM <mac_2/tx_buf/fsm_read/State/FSM> on signal <State[1:7]> with one-hot encoding.
Optimizing FSM <mac_3/tx_buf/fsm_read/State/FSM> on signal <State[1:7]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 0000001
 001   | 0000010
 010   | 0000100
 011   | 0001000
 100   | 0010000
 101   | 0100000
 110   | 1000000
-------------------
Analyzing FSM <FSM_9> for best encoding.
Optimizing FSM <mac_0/tx_buf/fsm_write/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_1/tx_buf/fsm_write/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_2/tx_buf/fsm_write/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_3/tx_buf/fsm_write/State/FSM> on signal <State[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 11    | 11
-------------------
Analyzing FSM <FSM_8> for best encoding.
Optimizing FSM <mac_0/rx_buf/fsm_read/count_priority0/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_1/rx_buf/fsm_read/count_priority0/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_2/rx_buf/fsm_read/count_priority0/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_3/rx_buf/fsm_read/count_priority0/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_0/rx_buf/fsm_read/count_priority1/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_1/rx_buf/fsm_read/count_priority1/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_2/rx_buf/fsm_read/count_priority1/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_3/rx_buf/fsm_read/count_priority1/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_0/rx_buf/fsm_read/count_priority2/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_1/rx_buf/fsm_read/count_priority2/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_2/rx_buf/fsm_read/count_priority2/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_3/rx_buf/fsm_read/count_priority2/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_0/rx_buf/fsm_read/count_priority3/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_1/rx_buf/fsm_read/count_priority3/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_2/rx_buf/fsm_read/count_priority3/State/FSM> on signal <State[1:2]> with user encoding.
Optimizing FSM <mac_3/rx_buf/fsm_read/count_priority3/State/FSM> on signal <State[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <FSM_7> for best encoding.
Optimizing FSM <mac_0/mac/rmon/ctrl/CurrentState/FSM> on signal <CurrentState[1:2]> with sequential encoding.
Optimizing FSM <mac_1/mac/rmon/ctrl/CurrentState/FSM> on signal <CurrentState[1:2]> with sequential encoding.
Optimizing FSM <mac_2/mac/rmon/ctrl/CurrentState/FSM> on signal <CurrentState[1:2]> with sequential encoding.
Optimizing FSM <mac_3/mac/rmon/ctrl/CurrentState/FSM> on signal <CurrentState[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 01
 0001  | 00
 0010  | 10
-------------------
Analyzing FSM <FSM_6> for best encoding.
Optimizing FSM <mac_0/mac/rmon/rx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_1/mac/rmon/rx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_2/mac/rmon/rx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_3/mac/rmon/rx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_0/mac/rmon/tx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_1/mac/rmon/tx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_2/mac/rmon/tx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
Optimizing FSM <mac_3/mac/rmon/tx_addr_gen/CurrentState/FSM> on signal <CurrentState[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 000
 0001  | 001
 0010  | 010
 0011  | 011
 0100  | 100
-------------------
Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <mac_0/mac/mac_tx/mac_tx_ctrl/Current_state/FSM> on signal <Current_state[1:15]> with one-hot encoding.
Optimizing FSM <mac_1/mac/mac_tx/mac_tx_ctrl/Current_state/FSM> on signal <Current_state[1:15]> with one-hot encoding.
Optimizing FSM <mac_2/mac/mac_tx/mac_tx_ctrl/Current_state/FSM> on signal <Current_state[1:15]> with one-hot encoding.
Optimizing FSM <mac_3/mac/mac_tx/mac_tx_ctrl/Current_state/FSM> on signal <Current_state[1:15]> with one-hot encoding.
--------------------------
 State | Encoding
--------------------------
 0000  | 000000000000100
 0001  | 000000000010000
 0010  | 000000001000000
 0011  | 000000100000000
 0100  | 000000000001000
 0101  | 000001000000000
 0110  | 000100000000000
 0111  | 000000000000010
 1000  | 000000000100000
 1001  | 001000000000000
 1010  | 010000000000000
 1011  | 000010000000000
 1100  | 100000000000000
 1101  | 000000000000001
 1110  | 000000010000000
--------------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <mac_0/mac/mac_rx/mac_rx_ff/read/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with user encoding.
Optimizing FSM <mac_1/mac/mac_rx/mac_rx_ff/read/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with user encoding.
Optimizing FSM <mac_2/mac/mac_rx/mac_rx_ff/read/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with user encoding.
Optimizing FSM <mac_3/mac/mac_rx/mac_rx_ff/read/Current_state_SYS/FSM> on signal <Current_state_SYS[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
-------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <mac_0/mac/mac_rx/mac_rx_ff/write/Current_state/FSM> on signal <Current_state[1:4]> with user encoding.
Optimizing FSM <mac_1/mac/mac_rx/mac_rx_ff/write/Current_state/FSM> on signal <Current_state[1:4]> with user encoding.
Optimizing FSM <mac_2/mac/mac_rx/mac_rx_ff/write/Current_state/FSM> on signal <Current_state[1:4]> with user encoding.
Optimizing FSM <mac_3/mac/mac_rx/mac_rx_ff/write/Current_state/FSM> on signal <Current_state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 1000  | 1000
 1001  | 1001
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <mac_0/mac/mac_rx/mac_rx_ctrl/Pause_current/FSM> on signal <Pause_current[1:3]> with sequential encoding.
Optimizing FSM <mac_1/mac/mac_rx/mac_rx_ctrl/Pause_current/FSM> on signal <Pause_current[1:3]> with sequential encoding.
Optimizing FSM <mac_2/mac/mac_rx/mac_rx_ctrl/Pause_current/FSM> on signal <Pause_current[1:3]> with sequential encoding.
Optimizing FSM <mac_3/mac/mac_rx/mac_rx_ctrl/Pause_current/FSM> on signal <Pause_current[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 000
 0001  | 001
 0010  | 010
 0011  | 011
 0100  | 100
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <mac_0/mac/mac_rx/mac_rx_ctrl/Current_state/FSM> on signal <Current_state[1:12]> with one-hot encoding.
Optimizing FSM <mac_1/mac/mac_rx/mac_rx_ctrl/Current_state/FSM> on signal <Current_state[1:12]> with one-hot encoding.
Optimizing FSM <mac_2/mac/mac_rx/mac_rx_ctrl/Current_state/FSM> on signal <Current_state[1:12]> with one-hot encoding.
Optimizing FSM <mac_3/mac/mac_rx/mac_rx_ctrl/Current_state/FSM> on signal <Current_state[1:12]> with one-hot encoding.
-----------------------
 State | Encoding
-----------------------
 0000  | 000000000001
 0001  | 000000000010
 0010  | 000000010000
 0011  | 000000100000
 0100  | 000001000000
 0111  | 001000000000
 1000  | 000000001000
 1001  | 000000000100
 1010  | 000100000000
 1011  | 100000000000
 1100  | 000010000000
 1101  | 010000000000
-----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <spi_to_epc/State/FSM> on signal <State[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 011
 011   | 110
 100   | 010
-------------------
WARNING:Xst:638 - in unit mac_tx_ff Conflict on KEEP property on signal Add_rd_add and Dout_reg_en Dout_reg_en signal will be lost.
Reading core <ram_8x8_dp.ngc>.
Reading core <ram_64x32.ngc>.
Reading core <ipcore_dir/fifo_2048_36.ngc>.
Reading core <ram_512x36_rx.ngc>.
Reading core <ram_512x36_tx.ngc>.
Reading core <fifo_512x36.ngc>.
Reading core <fifo_16x36.ngc>.
Loading core <ram_8x8_dp> for timing and area information for instance <ram>.
Loading core <ram_8x8_dp> for timing and area information for instance <ram>.
Loading core <ram_64x32> for timing and area information for instance <ram_rmon>.
Loading core <fifo_2048_36> for timing and area information for instance <tx_fifo>.
Loading core <ram_512x36_rx> for timing and area information for instance <ram>.
Loading core <ram_512x36_tx> for timing and area information for instance <ram>.
Loading core <fifo_512x36> for timing and area information for instance <rx_fifo>.
Loading core <fifo_16x36> for timing and area information for instance <fifo_a>.
Loading core <fifo_16x36> for timing and area information for instance <fifo_b>.
WARNING:Xst:1290 - Hierarchical block <mux_2> is unconnected in block <mux_traffic>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <mux_2> is unconnected in block <mux_traffic>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <mux_2> is unconnected in block <mux_traffic>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <mux_2> is unconnected in block <mux_traffic>.
   It will be removed from the design.
WARNING:Xst:1710 - FF/Latch <Din_34> (without init value) has a constant value of 0 in block <write>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Din_34> (without init value) has a constant value of 0 in block <write>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Din_34> (without init value) has a constant value of 0 in block <write>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Din_34> (without init value) has a constant value of 0 in block <write>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <UserWriteAddr_17> (without init value) has a constant value of 0 in block <write_mux>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <Dout_dl1_34> of sequential type is unconnected in block <read>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_3> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Dout_dl1_34> of sequential type is unconnected in block <read>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_3> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Dout_dl1_34> of sequential type is unconnected in block <read>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_3> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Dout_dl1_34> of sequential type is unconnected in block <read>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_3> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <IicSlaveAddr_0> of sequential type is unconnected in block <sfp>.
WARNING:Xst:2677 - Node <Dout_dl1_34> of sequential type is unconnected in block <mac_rx_ff_read>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Add_rd_reg_dl1_3> of sequential type is unconnected in block <mac_tx_ff>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 20
# ROMs                                                 : 1
 4x34-bit ROM                                          : 1
# Adders/Subtractors                                   : 80
 16-bit subtractor                                     : 4
 17-bit adder                                          : 17
 2-bit adder                                           : 2
 20-bit adder                                          : 1
 3-bit adder                                           : 5
 32-bit adder                                          : 5
 4-bit adder                                           : 1
 5-bit adder                                           : 1
 5-bit subtractor                                      : 8
 8-bit adder                                           : 4
 8-bit subtractor                                      : 8
 9-bit adder                                           : 24
# Counters                                             : 131
 10-bit down counter                                   : 4
 12-bit up counter                                     : 1
 16-bit down counter                                   : 4
 16-bit up counter                                     : 18
 16-bit updown counter                                 : 16
 17-bit up counter                                     : 1
 2-bit up counter                                      : 1
 24-bit up counter                                     : 2
 3-bit up counter                                      : 4
 32-bit up counter                                     : 1
 4-bit up counter                                      : 13
 5-bit up counter                                      : 8
 6-bit up counter                                      : 8
 6-bit updown counter                                  : 8
 7-bit up counter                                      : 2
 8-bit up counter                                      : 20
 8-bit updown counter                                  : 4
 9-bit up counter                                      : 16
# Registers                                            : 10719
 Flip-Flops                                            : 10719
# Comparators                                          : 280
 12-bit comparator less                                : 4
 16-bit comparator equal                               : 8
 16-bit comparator greatequal                          : 12
 16-bit comparator greater                             : 20
 16-bit comparator less                                : 53
 16-bit comparator lessequal                           : 12
 16-bit comparator not equal                           : 4
 17-bit comparator less                                : 16
 2-bit comparator greater                              : 2
 2-bit comparator less                                 : 3
 24-bit comparator greatequal                          : 2
 24-bit comparator less                                : 2
 3-bit comparator equal                                : 8
 3-bit comparator greatequal                           : 1
 3-bit comparator less                                 : 9
 3-bit comparator not equal                            : 4
 32-bit comparator less                                : 1
 4-bit comparator greatequal                           : 4
 4-bit comparator greater                              : 4
 4-bit comparator less                                 : 8
 4-bit comparator lessequal                            : 4
 48-bit comparator equal                               : 4
 5-bit comparator greatequal                           : 12
 5-bit comparator greater                              : 4
 5-bit comparator less                                 : 10
 5-bit comparator lessequal                            : 4
 6-bit comparator greatequal                           : 4
 6-bit comparator less                                 : 4
 7-bit comparator less                                 : 1
 8-bit comparator equal                                : 12
 8-bit comparator greatequal                           : 4
 8-bit comparator greater                              : 4
 9-bit comparator equal                                : 32
 9-bit comparator greater                              : 4
# Multiplexers                                         : 36
 1-bit 32-to-1 multiplexer                             : 1
 1-bit 4-to-1 multiplexer                              : 2
 17-bit 4-to-1 multiplexer                             : 9
 2-bit 4-to-1 multiplexer                              : 2
 3-bit 4-to-1 multiplexer                              : 4
 32-bit 4-to-1 multiplexer                             : 5
 32-bit 8-to-1 multiplexer                             : 1
 48-bit 8-to-1 multiplexer                             : 12
# Decoders                                             : 1
 1-of-8 decoder                                        : 1
# Xors                                                 : 689
 1-bit xor2                                            : 473
 1-bit xor3                                            : 96
 1-bit xor4                                            : 104
 1-bit xor6                                            : 16

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <Din_34> (without init value) has a constant value of 0 in block <mac_rx_ff_write>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <CurrentState_reg_0> of sequential type is unconnected in block <rmon_ctrl>.
WARNING:Xst:2677 - Node <Counter2_4> of sequential type is unconnected in block <one_sfp_als>.
WARNING:Xst:2677 - Node <Counter2_5> of sequential type is unconnected in block <one_sfp_als>.
WARNING:Xst:2677 - Node <Counter2_6> of sequential type is unconnected in block <one_sfp_als>.
WARNING:Xst:2677 - Node <Counter2_7> of sequential type is unconnected in block <one_sfp_als>.
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dpram.dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dpram.dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dpram.dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dpram.dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance B6 in unit B6 of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance B6 in unit B6 of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance B6 in unit B6 of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3_noinit.ram/dpram.dp9x9.ram of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance B6 in unit B6 of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram in unit U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp36x36.ram of type RAMB16_S36_S36 has been replaced by RAMB16
WARNING:Xst:2677 - Node <CurrentState_reg_1> of sequential type is unconnected in block <rmon_ctrl>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_9> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_8> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_6> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_5> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_4> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_3> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_1> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_0> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_reg_2> of sequential type is unconnected in block <mac_tx_ff>.
WARNING:Xst:2677 - Node <Current_state_MAC_9> of sequential type is unconnected in block <mac_tx_ff>.

Optimizing unit <top> ...

Optimizing unit <spi_to_epc> ...

Optimizing unit <timer> ...

Optimizing unit <phy_int_new> ...

Optimizing unit <mac_rx_ctrl> ...

Optimizing unit <broadcast_filter> ...

Optimizing unit <crc_chk> ...

Optimizing unit <mac_rx_ff_write> ...
INFO:Xst:2261 - The FF/Latch <Din_35> in Unit <mac_rx_ff_write> is equivalent to the following FF/Latch, which will be removed : <Packet_number_add_tmp> 

Optimizing unit <mac_rx_ff_read> ...

Optimizing unit <mac_tx_ctrl> ...

Optimizing unit <crc_gen> ...

Optimizing unit <flow_ctrl> ...

Optimizing unit <ramdon_gen> ...

Optimizing unit <rmon_addr_gen> ...

Optimizing unit <tx_buffer_fsm_new> ...

Optimizing unit <tx_write_fsm> ...

Optimizing unit <tx_read_fsm> ...

Optimizing unit <select_source> ...

Optimizing unit <pci_to_mac_fsm> ...

Optimizing unit <sram_write_mux> ...

Optimizing unit <sram_read_mux> ...

Optimizing unit <mdio_fsm> ...

Optimizing unit <iic_state_machine> ...

Optimizing unit <one_sfp_als> ...

Optimizing unit <reset_gen> ...

Optimizing unit <mac_rx_add_chk> ...

Optimizing unit <rx_ddr> ...

Optimizing unit <sram_read_new> ...

Optimizing unit <port_regs_1> ...

Optimizing unit <rmon_ctrl> ...

Optimizing unit <port_regs_2> ...

Optimizing unit <port_regs_3> ...

Optimizing unit <port_regs_4> ...

Optimizing unit <mac_mux> ...

Optimizing unit <mdio> ...

Optimizing unit <phy_new> ...

Optimizing unit <regs_int> ...

Optimizing unit <clock_ctrl_new> ...

Optimizing unit <mac_rx_ff_new> ...

Optimizing unit <mac_tx_ff> ...

Optimizing unit <rx_read_fsm> ...

Optimizing unit <sfp_als> ...

Optimizing unit <clock_gen> ...

Optimizing unit <rx_write_fsm> ...

Optimizing unit <tx_ddr> ...

Optimizing unit <sfp> ...

Optimizing unit <rx_packet_counters> ...

Optimizing unit <sram_ctrl> ...

Optimizing unit <bus> ...

Optimizing unit <mac_and_buf_1> ...

Optimizing unit <mac_and_buf_2> ...

Optimizing unit <mac_and_buf_3> ...

Optimizing unit <mac_and_buf_4> ...
WARNING:Xst:1710 - FF/Latch <arbiter/write_mux/UserWriteAddr_17> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <spi_to_epc/Read> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <arbiter/read_mux/SramAccessSelRegReg_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <arbiter/read_mux/SramAccessSelRegReg_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <arbiter/read_mux/SramAccessSelReg_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <arbiter/read_mux/SramAccessSelReg_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <serdes/rx/Ctrl_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mdio/MdioSel_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mdio/MdioSel_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <sfp/IicSlaveAddr_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/mac/mac_tx/mac_tx_ff/Fifo_da> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/PortTrafficClassMap_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst0FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst1FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst2FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDst3FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDstFilterNum_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDstFilterNum_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDstFilterNum_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/regs/MacDstFilterEna> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/mac/rmon/rx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/mac/rmon/tx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_0/mac/mac_tx/mac_tx_ctrl/MAC_tx_addr_rd> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/mac/mac_tx/mac_tx_ff/Fifo_da> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/PortTrafficClassMap_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst0FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst1FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst2FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDst3FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDstFilterNum_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDstFilterNum_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDstFilterNum_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/regs/MacDstFilterEna> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/mac/rmon/rx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/mac/rmon/tx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_1/mac/mac_tx/mac_tx_ctrl/MAC_tx_addr_rd> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/mac/mac_tx/mac_tx_ff/Fifo_da> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/PortTrafficClassMap_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst0FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst1FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst2FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDst3FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDstFilterNum_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDstFilterNum_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDstFilterNum_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/regs/MacDstFilterEna> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/mac/rmon/rx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/mac/rmon/tx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_2/mac/mac_tx/mac_tx_ctrl/MAC_tx_addr_rd> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/mac/mac_tx/mac_tx_ff/Fifo_da> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/PortTrafficClassMap_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3Filter_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst0FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst1FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst2FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_45> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_47> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_46> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_42> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_44> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_43> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_41> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_40> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_39> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_38> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_35> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_37> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_36> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_32> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_34> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_33> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_29> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_31> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_30> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_28> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_27> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_26> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_25> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_22> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_24> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_23> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_19> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_21> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_20> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_16> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_18> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_17> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_15> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_14> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_13> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_12> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_9> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_11> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_10> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_6> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_8> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_7> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_5> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_4> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDst3FilterMask_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDstFilterNum_0> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDstFilterNum_1> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDstFilterNum_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/regs/MacDstFilterEna> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/mac/rmon/rx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/mac/rmon/tx_addr_gen/Reg_drop_apply> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <mac_3/mac/mac_tx/mac_tx_ctrl/MAC_tx_addr_rd> of sequential type is unconnected in block <top>.

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_0> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_1> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_2> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_3> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_4> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_5> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_6> 
INFO:Xst:2261 - The FF/Latch <mac_3/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_3/mac/mac_rx/mac_rx_add_chk/data_dl1_7> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_0> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_1> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_2> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_3> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_4> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_5> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_6> 
INFO:Xst:2261 - The FF/Latch <mac_2/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_2/mac/mac_rx/mac_rx_add_chk/data_dl1_7> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_0> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_1> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_2> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_3> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_4> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_5> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_6> 
INFO:Xst:2261 - The FF/Latch <mac_1/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_1/mac/mac_rx/mac_rx_add_chk/data_dl1_7> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_0> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_0> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_1> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_1> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_2> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_2> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_3> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_3> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_4> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_4> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_5> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_5> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_6> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_6> 
INFO:Xst:2261 - The FF/Latch <mac_0/mac/mac_rx/mac_rx_ff/write/Fifo_data_dl1_7> in Unit <top> is equivalent to the following FF/Latch, which will be removed : <mac_0/mac/mac_rx/mac_rx_add_chk/data_dl1_7> 
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 35.
INFO:Xst:2260 - The FF/Latch <sram/address[0].address/AD_FDC_W_bar> in Unit <top> is equivalent to the following 23 FFs/Latches : <sram/address[1].address/AD_FDC_W_bar> <sram/address[2].address/AD_FDC_W_bar> <sram/address[3].address/AD_FDC_W_bar> <sram/address[4].address/AD_FDC_W_bar> <sram/address[5].address/AD_FDC_W_bar> <sram/address[6].address/AD_FDC_W_bar> <sram/address[7].address/AD_FDC_W_bar> <sram/address[8].address/AD_FDC_W_bar> <sram/address[9].address/AD_FDC_W_bar> <sram/address[10].address/AD_FDC_W_bar> <sram/address[11].address/AD_FDC_W_bar> <sram/address[12].address/AD_FDC_W_bar> <sram/address[13].address/AD_FDC_W_bar> <sram/address[14].address/AD_FDC_W_bar> <sram/address[15].address/AD_FDC_W_bar> <sram/address[16].address/AD_FDC_W_bar> <sram/address[17].address/AD_FDC_W_bar> <sram/address[18].address/AD_FDC_W_bar> <sram/address[19].address/AD_FDC_W_bar> <sram/INST_BW_FD3> <sram/INST_BW_FD2> <sram/INST_BW_FD1> <sram/INST_BW_FD0> 
INFO:Xst:2260 - The FF/Latch <serdes/tx/ddr_ctrl[0].write/FDC_ENVOI> in Unit <top> is equivalent to the following 19 FFs/Latches : <serdes/tx/ddr_ctrl[1].write/FDC_ENVOI> <serdes/tx/ddr_ctrl[2].write/FDC_ENVOI> <serdes/tx/ddr_ctrl[3].write/FDC_ENVOI> <serdes/tx/ddr_data[0].write/FDC_ENVOI> <serdes/tx/ddr_data[1].write/FDC_ENVOI> <serdes/tx/ddr_data[2].write/FDC_ENVOI> <serdes/tx/ddr_data[3].write/FDC_ENVOI> <serdes/tx/ddr_data[4].write/FDC_ENVOI> <serdes/tx/ddr_data[5].write/FDC_ENVOI> <serdes/tx/ddr_data[6].write/FDC_ENVOI> <serdes/tx/ddr_data[7].write/FDC_ENVOI> <serdes/tx/ddr_data[8].write/FDC_ENVOI> <serdes/tx/ddr_data[9].write/FDC_ENVOI> <serdes/tx/ddr_data[10].write/FDC_ENVOI> <serdes/tx/ddr_data[11].write/FDC_ENVOI> <serdes/tx/ddr_data[12].write/FDC_ENVOI> <serdes/tx/ddr_data[13].write/FDC_ENVOI> <serdes/tx/ddr_data[14].write/FDC_ENVOI> <serdes/tx/ddr_data[15].write/FDC_ENVOI> 
INFO:Xst:2260 - The FF/Latch <sram/write[0].write/FDC_ENVOI> in Unit <top> is equivalent to the following 35 FFs/Latches : <sram/write[1].write/FDC_ENVOI> <sram/write[2].write/FDC_ENVOI> <sram/write[3].write/FDC_ENVOI> <sram/write[4].write/FDC_ENVOI> <sram/write[5].write/FDC_ENVOI> <sram/write[6].write/FDC_ENVOI> <sram/write[7].write/FDC_ENVOI> <sram/write[8].write/FDC_ENVOI> <sram/write[9].write/FDC_ENVOI> <sram/write[10].write/FDC_ENVOI> <sram/write[11].write/FDC_ENVOI> <sram/write[12].write/FDC_ENVOI> <sram/write[13].write/FDC_ENVOI> <sram/write[14].write/FDC_ENVOI> <sram/write[15].write/FDC_ENVOI> <sram/write[16].write/FDC_ENVOI> <sram/write[17].write/FDC_ENVOI> <sram/write[18].write/FDC_ENVOI> <sram/write[19].write/FDC_ENVOI> <sram/write[20].write/FDC_ENVOI> <sram/write[21].write/FDC_ENVOI> <sram/write[22].write/FDC_ENVOI> <sram/write[23].write/FDC_ENVOI> <sram/write[24].write/FDC_ENVOI> <sram/write[25].write/FDC_ENVOI> <sram/write[26].write/FDC_ENVOI> <sram/write[27].write/FDC_ENVOI>
   <sram/write[28].write/FDC_ENVOI> <sram/write[29].write/FDC_ENVOI> <sram/write[30].write/FDC_ENVOI> <sram/write[31].write/FDC_ENVOI> <sram/write[32].write/FDC_ENVOI> <sram/write[33].write/FDC_ENVOI> <sram/write[34].write/FDC_ENVOI> <sram/write[35].write/FDC_ENVOI> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/wpntr/count_d1_3> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/wpntr/count_d1_3_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_0> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_0_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_1_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/rpntr/count_d1_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/rpntr/count_d1_2_1> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/rd_rst_reg_2> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwss.wsts/ram_full_i> 
FlipFlop spi_to_epc/RegAddr_1 has been replicated 1 time(s)
FlipFlop spi_to_epc/RegAddr_2 has been replicated 1 time(s)
FlipFlop spi_to_epc/RegAddr_3 has been replicated 1 time(s)
FlipFlop spi_to_epc/RegAddr_5 has been replicated 1 time(s)

Final Macro Processing ...

Processing Unit <top> :
	Found 2-bit shift register for signal <arbiter/read_mux/SramAccessRegReg>.
	Found 5-bit shift register for signal <sram/USER_DV_Shift_4>.
Unit <top> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 10648
 Flip-Flops                                            : 10648
# Shift Registers                                      : 2
 2-bit shift register                                  : 1
 5-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 318

Cell Usage :
# BELS                             : 19053
#      GND                         : 71
#      INV                         : 327
#      LUT1                        : 799
#      LUT2                        : 1493
#      LUT2_D                      : 6
#      LUT2_L                      : 10
#      LUT3                        : 3982
#      LUT3_D                      : 9
#      LUT3_L                      : 16
#      LUT4                        : 6024
#      LUT4_D                      : 25
#      LUT4_L                      : 150
#      MUXCY                       : 2710
#      MUXF5                       : 1223
#      MUXF6                       : 260
#      MUXF7                       : 33
#      MUXF8                       : 8
#      VCC                         : 17
#      XORCY                       : 1890
# FlipFlops/Latches                : 11464
#      FD                          : 84
#      FDC                         : 927
#      FDCE                        : 8207
#      FDCE_1                      : 4
#      FDCPE                       : 544
#      FDDRRSE                     : 98
#      FDE                         : 795
#      FDP                         : 72
#      FDPE                        : 587
#      FDR                         : 77
#      FDS                         : 12
#      FDS_1                       : 1
#      IFDDRCPE                    : 20
#      IFDDRRSE                    : 36
# RAMS                             : 112
#      RAM16X1D                    : 72
#      RAMB16                      : 40
# Shift Registers                  : 2
#      SRL16                       : 2
# Clock Buffers                    : 7
#      BUFG                        : 7
# IO Buffers                       : 254
#      IBUF                        : 71
#      IBUFDS                      : 1
#      IBUFG                       : 4
#      IOBUF                       : 5
#      OBUF                        : 83
#      OBUFDS                      : 2
#      OBUFT                       : 88
# DCMs                             : 2
#      DCM                         : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s4000fg676-5 

 Number of Slices:                     9802  out of  27648    35%  
 Number of Slice Flip Flops:          11400  out of  55296    20%  
 Number of 4 input LUTs:              12987  out of  55296    23%  
    Number used as logic:             12841
    Number used as Shift registers:       2
    Number used as RAMs:                144
 Number of IOs:                         318
 Number of bonded IOBs:                 313  out of    489    64%  
    IOB Flip Flops:                      64
 Number of BRAMs:                        40  out of     96    41%  
 Number of GCLKs:                         7  out of      8    87%  
 Number of DCMs:                          2  out of      4    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------------------+-------------------------------------------------------+-------+
Clock Signal                                                 | Clock buffer(FF name)                                 | Load  |
-------------------------------------------------------------+-------------------------------------------------------+-------+
BusSpiSck                                                    | IBUF                                                  | 58    |
BusRxClock_p                                                 | IBUFDS+BUFG                                           | 7186  |
spi_to_epc/Write                                             | NONE(timer/LoadMicrosecond_31)                        | 2548  |
BusRxClock_p                                                 | clock_gen/dcm/DCM_INST:CLK0                           | 272   |
SramCq                                                       | sram/read_clock/dcm/DCM_INST:CLK0                     | 108   |
Phy0RxClk                                                    | IBUFG+BUFG                                            | 356   |
mac_0/mac/mac_rx/mac_rx_ff/write/Packet_number_add           | NONE(mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)| 1     |
Phy0TxClk                                                    | IBUF                                                  | 1     |
mac_0/mac/rmon/ctrl/CPU_rd_apply_reg                         | NONE(mac_0/mac/regs_int/RmonDout_0)                   | 32    |
mac_0/mac/regs_int/RmonReadx(mac_0/mac/regs_int/RmonReadx1:O)| NONE(*)(mac_0/mac/regs_int/short_impulse/a)           | 1     |
Phy1RxClk                                                    | IBUFG+BUFG                                            | 356   |
mac_1/mac/mac_rx/mac_rx_ff/write/Packet_number_add           | NONE(mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)| 1     |
Phy1TxClk                                                    | IBUF                                                  | 1     |
mac_1/mac/rmon/ctrl/CPU_rd_apply_reg                         | NONE(mac_1/mac/regs_int/RmonDout_0)                   | 32    |
mac_1/mac/regs_int/RmonReadx(mac_1/mac/regs_int/RmonReadx1:O)| NONE(*)(mac_1/mac/regs_int/short_impulse/a)           | 1     |
Phy2RxClk                                                    | IBUFG+BUFG                                            | 356   |
mac_2/mac/mac_rx/mac_rx_ff/write/Packet_number_add           | NONE(mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)| 1     |
Phy2TxClk                                                    | IBUF                                                  | 1     |
mac_2/mac/rmon/ctrl/CPU_rd_apply_reg                         | NONE(mac_2/mac/regs_int/RmonDout_0)                   | 32    |
mac_2/mac/regs_int/RmonReadx(mac_2/mac/regs_int/RmonReadx1:O)| NONE(*)(mac_2/mac/regs_int/short_impulse/a)           | 1     |
Phy3RxClk                                                    | IBUFG+BUFG                                            | 356   |
mac_3/mac/mac_rx/mac_rx_ff/write/Packet_number_add           | NONE(mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)| 1     |
Phy3TxClk                                                    | IBUF                                                  | 1     |
mac_3/mac/rmon/ctrl/CPU_rd_apply_reg                         | NONE(mac_3/mac/regs_int/RmonDout_0)                   | 32    |
mac_3/mac/regs_int/RmonReadx(mac_3/mac/regs_int/RmonReadx1:O)| NONE(*)(mac_3/mac/regs_int/short_impulse/a)           | 1     |
-------------------------------------------------------------+-------------------------------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+-------+
Control Signal                                                                                                   | Buffer(FF name)                                                        | Load  |
-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+-------+
BusReady_OBUF(XST_GND:G)                                                                                         | NONE(mac_0/rx_buf/fsm_read/count_priority0/AddrCalc_0)                 | 586   |
bus/packet_counters/Reset_inv1_INV_0_4(bus/packet_counters/Reset_inv1_INV_0_4:O)                                 | NONE(mac_3/mac/regs_int/CPU_rd_apply)                                  | 495   |
bus/packet_counters/Reset_inv1_INV_0_5(bus/packet_counters/Reset_inv1_INV_0_5:O)                                 | NONE(mac_2/mac/rmon/tx_addr_gen/Pkt_length_rmon_dl1_0)                 | 495   |
bus/packet_counters/Reset_inv1_INV_0_6(bus/packet_counters/Reset_inv1_INV_0_6:O)                                 | NONE(mac_1/regs/MacReset)                                              | 495   |
bus/packet_counters/Reset_inv1_INV_0_7(bus/packet_counters/Reset_inv1_INV_0_7:O)                                 | NONE(mac_1/mac/regs_int/CPU_rd_apply)                                  | 495   |
bus/packet_counters/Reset_inv1_INV_0_8(bus/packet_counters/Reset_inv1_INV_0_8:O)                                 | NONE(mac_0/regs/MacReset)                                              | 495   |
bus/Reset_inv(bus/packet_counters/Reset_inv1_INV_0:O)                                                            | NONE(mac_0/mac/regs_int/CPU_rd_apply)                                  | 494   |
bus/packet_counters/Reset_inv1_INV_0_1(bus/packet_counters/Reset_inv1_INV_0_1:O)                                 | NONE(bus/BusPacketStrobe)                                              | 494   |
bus/packet_counters/Reset_inv1_INV_0_3(bus/packet_counters/Reset_inv1_INV_0_3:O)                                 | NONE(mac_3/regs/MacReset)                                              | 494   |
mac_0/rx_buf/fsm_read/Reset_inv(mac_0/rx_buf/fsm_write/Reset_inv431_INV_0:O)                                     | NONE(mac_0/mac/mac_rx/mac_rx_ff/read/Add_rd_0)                         | 435   |
mac_0/rx_buf/fsm_write/Reset_inv431_INV_0_2(mac_0/rx_buf/fsm_write/Reset_inv431_INV_0_2:O)                       | NONE(mac_0/mac/clock_ctrl/MacTxClockEna)                               | 435   |
mac_1/rx_buf/fsm_read/Reset_inv(mac_1/rx_buf/fsm_write/Reset_inv431_INV_0:O)                                     | NONE(mac_1/mac/mac_rx/mac_rx_ff/read/Add_rd_0)                         | 435   |
mac_1/rx_buf/fsm_write/Reset_inv431_INV_0_2(mac_1/rx_buf/fsm_write/Reset_inv431_INV_0_2:O)                       | NONE(mac_1/mac/clock_ctrl/MacTxClockEna)                               | 435   |
mac_2/rx_buf/fsm_read/Reset_inv(mac_2/rx_buf/fsm_write/Reset_inv431_INV_0:O)                                     | NONE(mac_2/mac/mac_rx/mac_rx_ff/read/Add_rd_0)                         | 435   |
mac_2/rx_buf/fsm_write/Reset_inv431_INV_0_2(mac_2/rx_buf/fsm_write/Reset_inv431_INV_0_2:O)                       | NONE(mac_2/mac/clock_ctrl/MacTxClockEna)                               | 435   |
mac_3/rx_buf/fsm_read/Reset_inv(mac_3/rx_buf/fsm_write/Reset_inv431_INV_0:O)                                     | NONE(mac_3/mac/mac_rx/mac_rx_ff/read/Add_rd_0)                         | 435   |
mac_3/rx_buf/fsm_write/Reset_inv431_INV_0_2(mac_3/rx_buf/fsm_write/Reset_inv431_INV_0_2:O)                       | NONE(mac_3/mac/clock_ctrl/MacTxClockEna)                               | 435   |
mac_0/rx_buf/fsm_write/Reset_inv431_INV_0_1(mac_0/rx_buf/fsm_write/Reset_inv431_INV_0_1:O)                       | NONE(mac_0/mac/mac_rx/mac_rx_ctrl/Crs_dv)                              | 434   |
mac_1/rx_buf/fsm_write/Reset_inv431_INV_0_1(mac_1/rx_buf/fsm_write/Reset_inv431_INV_0_1:O)                       | NONE(mac_1/mac/mac_rx/mac_rx_ctrl/Crs_dv)                              | 434   |
mac_2/rx_buf/fsm_write/Reset_inv431_INV_0_1(mac_2/rx_buf/fsm_write/Reset_inv431_INV_0_1:O)                       | NONE(mac_2/mac/mac_rx/mac_rx_ctrl/Crs_dv)                              | 434   |
mac_3/rx_buf/fsm_write/Reset_inv431_INV_0_1(mac_3/rx_buf/fsm_write/Reset_inv431_INV_0_1:O)                       | NONE(mac_3/mac/mac_rx/mac_rx_ctrl/Crs_dv)                              | 434   |
bus/packet_counters/Reset_inv1_INV_0_2(bus/packet_counters/Reset_inv1_INV_0_2:O)                                 | NONE(sfp/IicDataWriteReg_0)                                            | 381   |
mdio/MdioOpcode_Acst_inv(mdio/fsm/Reset_inv1_INV_0:O)                                                            | NONE(mdio/CountMdioClock_0)                                            | 42    |
arbiter/write_mux/UserWrite(arbiter/write_mux/UserWrite:Q)                                                       | NONE(sram/write[0].write/FDC_ENVOI)                                    | 36    |
bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_reg<0>(bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_reg_0:Q)                    | NONE(bus/fifo_a/BU2/U0/grf.rf/mem/gdm.dm/dout_i_0)                     | 36    |
bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_reg<0>(bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_reg_0:Q)                    | NONE(bus/fifo_b/BU2/U0/grf.rf/mem/gdm.dm/dout_i_0)                     | 36    |
mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 35    |
mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 35    |
mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 35    |
mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 35    |
mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 29    |
mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 29    |
mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 29    |
mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)| NONE(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.rd/grss.gdc.dc/dc/count_0) | 29    |
phy/MdioResetStart(phy/MdioResetStart1:O)                                                                        | NONE(phy/mdio/Count_0)                                                 | 26    |
phy/PhyResetStart(phy/PhyResetStart_or0000235_f5:O)                                                              | NONE(phy/phy/Count_0)                                                  | 26    |
mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 25    |
mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 25    |
mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 25    |
mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 25    |
mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 21    |
mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 21    |
mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 21    |
mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)| 21    |
BusReady_inv(XST_VCC:P)                                                                                          | NONE(serdes/tx/ddr_ctrl[0].write/FDC_ENVOI)                            | 20    |
bus/fifo_a/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(bus/fifo_a/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)                    | NONE(bus/fifo_a/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)          | 15    |
bus/fifo_b/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(bus/fifo_b/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)                    | NONE(bus/fifo_b/BU2/U0/grf.rf/gl0.wr/gwss.wsts/ram_full_fb_i)          | 15    |
bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)                    | NONE(bus/fifo_a/BU2/U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i)         | 14    |
bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_reg<2>(bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_reg_2:Q)                    | NONE(bus/fifo_b/BU2/U0/grf.rf/gl0.rd/grss.rsts/ram_empty_fb_i)         | 14    |
BusReset                                                                                                         | IBUF                                                                   | 13    |
sfp/als/als_sfp0/Rst_inv(sfp/als/als_sfp0/Rst_inv1:O)                                                            | NONE(sfp/als/als_sfp0/Counter_0)                                       | 11    |
sfp/als/als_sfp1/Rst_inv(sfp/als/als_sfp1/Rst_inv1:O)                                                            | NONE(sfp/als/als_sfp1/Counter_0)                                       | 11    |
sfp/als/als_sfp2/Rst_inv(sfp/als/als_sfp2/Rst_inv1:O)                                                            | NONE(sfp/als/als_sfp2/Counter_0)                                       | 11    |
sfp/als/als_sfp3/Rst_inv(sfp/als/als_sfp3/Rst_inv1:O)                                                            | NONE(sfp/als/als_sfp3/Counter_0)                                       | 11    |
sfp/als/als_sfp0/Clock2Reset_inv(sfp/als/als_sfp0/Clock2Reset_inv1:O)                                            | NONE(sfp/als/als_sfp0/Counter2_0)                                      | 4     |
sfp/als/als_sfp1/Clock2Reset_inv(sfp/als/als_sfp1/Clock2Reset_inv1:O)                                            | NONE(sfp/als/als_sfp1/Counter2_0)                                      | 4     |
sfp/als/als_sfp2/Clock2Reset_inv(sfp/als/als_sfp2/Clock2Reset_inv1:O)                                            | NONE(sfp/als/als_sfp2/Counter2_0)                                      | 4     |
sfp/als/als_sfp3/Clock2Reset_inv(sfp/als/als_sfp3/Clock2Reset_inv1:O)                                            | NONE(sfp/als/als_sfp3/Counter2_0)                                      | 4     |
bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_comb(bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)                      | NONE(bus/fifo_a/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                     | 2     |
bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_comb(bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)                      | NONE(bus/fifo_b/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)                     | 2     |
mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O)  | NONE(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0)           | 2     |
bus/fifo_a/BU2/U0/grf.rf/rstblk/wr_rst_comb(bus/fifo_a/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)                      | NONE(bus/fifo_a/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)                     | 1     |
bus/fifo_b/BU2/U0/grf.rf/rstblk/wr_rst_comb(bus/fifo_b/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)                      | NONE(bus/fifo_b/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)                     | 1     |
mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_0/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_0/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_1/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_1/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_2/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_2/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_3/rx_buf/rx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O)  | NONE(mac_3/tx_buf/tx_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1)           | 1     |
mdio/fsm/Busy(mdio/fsm/Busy:Q)                                                                                   | NONE(mdio/MdioStart)                                                   | 1     |
sfp/fsm/Busy(sfp/fsm/Busy:Q)                                                                                     | NONE(sfp/IicStart)                                                     | 1     |
-----------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 27.139ns (Maximum Frequency: 36.847MHz)
   Minimum input arrival time before clock: 9.843ns
   Maximum output required time after clock: 9.126ns
   Maximum combinational path delay: 11.846ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'BusSpiSck'
  Clock period: 27.139ns (frequency: 36.847MHz)
  Total number of paths / destination ports: 5567 / 59
-------------------------------------------------------------------------
Delay:               13.569ns (Levels of Logic = 12)
  Source:            spi_to_epc/RegAddr_0 (FF)
  Destination:       spi_to_epc/SpiMiso (FF)
  Source Clock:      BusSpiSck rising
  Destination Clock: BusSpiSck falling

  Data Path: spi_to_epc/RegAddr_0 to spi_to_epc/SpiMiso
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q           371   0.626   3.285  spi_to_epc/RegAddr_0 (spi_to_epc/RegAddr_0)
     LUT3_D:I2->O         31   0.479   1.629  mac_3/mac/regs_int/MuxData_cmp_eq002811 (mac_3/mac/regs_int/N3)
     LUT3:I2->O            1   0.479   0.976  mac_3/bus/SysDout<1>1 (mac_3/bus/SysDout<1>1)
     LUT4:I0->O            1   0.479   0.704  mac_3/bus/SysDout<1>11 (mac_3/bus/SysDout<1>11)
     LUT4:I3->O            1   0.479   0.740  mac_3/bus/SysDout<1>190_SW0 (N2471)
     LUT4:I2->O            1   0.479   0.000  spi_to_epc/Mmux__varindex0000_1529 (spi_to_epc/Mmux__varindex0000_1529)
     MUXF5:I1->O           1   0.314   0.000  spi_to_epc/Mmux__varindex0000_14_f5_9 (spi_to_epc/Mmux__varindex0000_14_f510)
     MUXF6:I0->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_12_f6_7 (spi_to_epc/Mmux__varindex0000_12_f68)
     MUXF7:I1->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_11_f7_1 (spi_to_epc/Mmux__varindex0000_11_f72)
     MUXF8:I0->O           1   0.298   0.740  spi_to_epc/Mmux__varindex0000_9_f8_1 (spi_to_epc/Mmux__varindex0000_9_f82)
     LUT3:I2->O            1   0.479   0.000  spi_to_epc/Mmux__varindex0000_6 (spi_to_epc/Mmux__varindex0000_6)
     MUXF5:I0->O           1   0.314   0.000  spi_to_epc/Mmux__varindex0000_4_f5 (spi_to_epc/Mmux__varindex0000_4_f5)
     MUXF6:I0->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_2_f6 (spi_to_epc/_varindex0000)
     FDS_1:D                   0.176          spi_to_epc/SpiMiso
    ----------------------------------------
    Total                     13.569ns (5.496ns logic, 8.073ns route)
                                       (40.5% logic, 59.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'BusRxClock_p'
  Clock period: 13.559ns (frequency: 73.749MHz)
  Total number of paths / destination ports: 221355 / 14296
-------------------------------------------------------------------------
Delay:               13.559ns (Levels of Logic = 14)
  Source:            mac_0/mac/mac_tx/mac_tx_ctrl/Tx_pkt_length_rmon_1 (FF)
  Destination:       mac_0/mac/mac_tx/crc_gen/CRC_reg_14 (FF)
  Source Clock:      BusRxClock_p rising
  Destination Clock: BusRxClock_p rising

  Data Path: mac_0/mac/mac_tx/mac_tx_ctrl/Tx_pkt_length_rmon_1 to mac_0/mac/mac_tx/crc_gen/CRC_reg_14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             3   0.626   1.066  mac_0/mac/mac_tx/mac_tx_ctrl/Tx_pkt_length_rmon_1 (mac_0/mac/mac_tx/mac_tx_ctrl/Tx_pkt_length_rmon_1)
     LUT2:I0->O            1   0.479   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_lut<0> (mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_lut<0>)
     MUXCY:S->O            1   0.435   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<0> (mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<0>)
     MUXCY:CI->O           1   0.056   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<1> (mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<1>)
     MUXCY:CI->O           1   0.056   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<2> (mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<2>)
     MUXCY:CI->O           1   0.056   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<3> (mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<3>)
     MUXCY:CI->O           1   0.264   0.851  mac_0/mac/mac_tx/mac_tx_ctrl/Mcompar_Src_MAC_ptr_cmp_ge0000_cy<4> (mac_0/mac/mac_tx/mac_tx_ctrl/Src_MAC_ptr_cmp_ge0000)
     LUT3:I1->O           12   0.479   0.973  mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp_and00001 (mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp_and0000)
     LUT4:I3->O            6   0.479   1.148  mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<2>61 (mac_0/mac/mac_tx/mac_tx_ctrl/N56)
     LUT4:I0->O            1   0.479   0.000  mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<5>811 (mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<5>811)
     MUXF5:I1->O           3   0.314   0.941  mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<5>81_f5 (mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<5>81)
     LUT2:I1->O            6   0.479   1.023  mac_0/mac/mac_tx/mac_tx_ctrl/TxD_tmp<5>86 (mac_0/mac/mac_tx/Frame_data<5>)
     LUT4:I1->O            2   0.479   1.040  mac_0/mac/mac_tx/crc_gen/Mxor_CRC_reg_xor0052_Result1 (mac_0/mac/mac_tx/crc_gen/CRC_reg_xor0052)
     LUT4:I0->O            1   0.479   0.704  mac_0/mac/mac_tx/crc_gen/Mmux_CRC_reg_mux000018_SW0 (N2162)
     LUT4:I3->O            1   0.479   0.000  mac_0/mac/mac_tx/crc_gen/Mmux_CRC_reg_mux000018 (mac_0/mac/mac_tx/crc_gen/CRC_reg_mux0000<17>)
     FDPE:D                    0.176          mac_0/mac/mac_tx/crc_gen/CRC_reg_14
    ----------------------------------------
    Total                     13.559ns (5.814ns logic, 7.745ns route)
                                       (42.9% logic, 57.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'SramCq'
  Clock period: 2.966ns (frequency: 337.189MHz)
  Total number of paths / destination ports: 36 / 36
-------------------------------------------------------------------------
Delay:               1.483ns (Levels of Logic = 0)
  Source:            sram/read[0].read/RD_FDC (UNKNOWN)
  Destination:       sram/read[0].read/RD_FDC_D0_C_RLMT (FF)
  Source Clock:      SramCq rising +-32
  Destination Clock: SramCq falling +-32

  Data Path: sram/read[0].read/RD_FDC to sram/read[0].read/RD_FDC_D0_C_RLMT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IFDDRRSE:C0->Q0       1   0.626   0.681  sram/read[0].read/RD_FDC (sram/read[0].read/D0_CAPT)
     FDC:D                     0.176          sram/read[0].read/RD_FDC_D0_C_RLMT
    ----------------------------------------
    Total                      1.483ns (0.802ns logic, 0.681ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy0RxClk'
  Clock period: 13.007ns (frequency: 76.879MHz)
  Total number of paths / destination ports: 9294 / 713
-------------------------------------------------------------------------
Delay:               13.007ns (Levels of Logic = 8)
  Source:            mac_0/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (FF)
  Destination:       mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr (FF)
  Source Clock:      Phy0RxClk rising
  Destination Clock: Phy0RxClk rising

  Data Path: mac_0/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 to mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.626   1.078  mac_0/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (mac_0/mac/mac_rx/mac_rx_ctrl/IFG_counter_4)
     LUT2:I0->O            1   0.479   0.851  mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002411 (mac_0/mac/mac_rx/mac_rx_ctrl/N9)
     LUT4:I1->O            1   0.479   0.976  mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289 (mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289)
     LUT4:I0->O            1   0.479   0.851  mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865 (mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865)
     LUT3:I1->O            2   0.479   1.040  mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq00028148 (mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002)
     LUT4:I0->O            2   0.479   0.804  mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_FSM_FFd12-In (mac_0/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0014)
     LUT4:I2->O            2   0.479   1.040  mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001292 (mac_0/mac/mac_rx/mac_rx_ctrl/N19)
     LUT3:I0->O            1   0.479   0.704  mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001_SW1 (N3804)
     LUT4:I3->O            1   0.479   0.681  mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001 (mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001)
     FDCE:CE                   0.524          mac_0/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
    ----------------------------------------
    Total                     13.007ns (4.982ns logic, 8.025ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_0/mac/mac_rx/mac_rx_ff/write/Packet_number_add'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Destination:       mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Source Clock:      mac_0/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising
  Destination Clock: mac_0/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising

  Data Path: mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg to mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)
     INV:I->O              1   0.479   0.681  mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not00011_INV_0 (mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not0001)
     FDC:D                     0.176          mac_0/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy0TxClk'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_0/mac/clock_ctrl/shorter/a (FF)
  Destination:       mac_0/mac/clock_ctrl/shorter/a (FF)
  Source Clock:      Phy0TxClk rising
  Destination Clock: Phy0TxClk rising

  Data Path: mac_0/mac/clock_ctrl/shorter/a to mac_0/mac/clock_ctrl/shorter/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_0/mac/clock_ctrl/shorter/a (mac_0/mac/clock_ctrl/shorter/a)
     INV:I->O              1   0.479   0.681  mac_0/mac/clock_ctrl/shorter/a_not00011_INV_0 (mac_0/mac/clock_ctrl/shorter/a_not0001)
     FDC:D                     0.176          mac_0/mac/clock_ctrl/shorter/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_0/mac/regs_int/RmonReadx'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_0/mac/regs_int/short_impulse/a (FF)
  Destination:       mac_0/mac/regs_int/short_impulse/a (FF)
  Source Clock:      mac_0/mac/regs_int/RmonReadx rising
  Destination Clock: mac_0/mac/regs_int/RmonReadx rising

  Data Path: mac_0/mac/regs_int/short_impulse/a to mac_0/mac/regs_int/short_impulse/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_0/mac/regs_int/short_impulse/a (mac_0/mac/regs_int/short_impulse/a)
     INV:I->O              1   0.479   0.681  mac_0/mac/regs_int/short_impulse/a_not00011_INV_0 (mac_0/mac/regs_int/short_impulse/a_not0001)
     FDC:D                     0.176          mac_0/mac/regs_int/short_impulse/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy1RxClk'
  Clock period: 13.007ns (frequency: 76.879MHz)
  Total number of paths / destination ports: 9294 / 713
-------------------------------------------------------------------------
Delay:               13.007ns (Levels of Logic = 8)
  Source:            mac_1/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (FF)
  Destination:       mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr (FF)
  Source Clock:      Phy1RxClk rising
  Destination Clock: Phy1RxClk rising

  Data Path: mac_1/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 to mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.626   1.078  mac_1/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (mac_1/mac/mac_rx/mac_rx_ctrl/IFG_counter_4)
     LUT2:I0->O            1   0.479   0.851  mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002411 (mac_1/mac/mac_rx/mac_rx_ctrl/N9)
     LUT4:I1->O            1   0.479   0.976  mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289 (mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289)
     LUT4:I0->O            1   0.479   0.851  mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865 (mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865)
     LUT3:I1->O            2   0.479   1.040  mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq00028148 (mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002)
     LUT4:I0->O            2   0.479   0.804  mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_FSM_FFd12-In (mac_1/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0014)
     LUT4:I2->O            2   0.479   1.040  mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001292 (mac_1/mac/mac_rx/mac_rx_ctrl/N19)
     LUT3:I0->O            1   0.479   0.704  mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001_SW1 (N3802)
     LUT4:I3->O            1   0.479   0.681  mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001 (mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001)
     FDCE:CE                   0.524          mac_1/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
    ----------------------------------------
    Total                     13.007ns (4.982ns logic, 8.025ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_1/mac/mac_rx/mac_rx_ff/write/Packet_number_add'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Destination:       mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Source Clock:      mac_1/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising
  Destination Clock: mac_1/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising

  Data Path: mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg to mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)
     INV:I->O              1   0.479   0.681  mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not00011_INV_0 (mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not0001)
     FDC:D                     0.176          mac_1/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy1TxClk'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_1/mac/clock_ctrl/shorter/a (FF)
  Destination:       mac_1/mac/clock_ctrl/shorter/a (FF)
  Source Clock:      Phy1TxClk rising
  Destination Clock: Phy1TxClk rising

  Data Path: mac_1/mac/clock_ctrl/shorter/a to mac_1/mac/clock_ctrl/shorter/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_1/mac/clock_ctrl/shorter/a (mac_1/mac/clock_ctrl/shorter/a)
     INV:I->O              1   0.479   0.681  mac_1/mac/clock_ctrl/shorter/a_not00011_INV_0 (mac_1/mac/clock_ctrl/shorter/a_not0001)
     FDC:D                     0.176          mac_1/mac/clock_ctrl/shorter/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_1/mac/regs_int/RmonReadx'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_1/mac/regs_int/short_impulse/a (FF)
  Destination:       mac_1/mac/regs_int/short_impulse/a (FF)
  Source Clock:      mac_1/mac/regs_int/RmonReadx rising
  Destination Clock: mac_1/mac/regs_int/RmonReadx rising

  Data Path: mac_1/mac/regs_int/short_impulse/a to mac_1/mac/regs_int/short_impulse/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_1/mac/regs_int/short_impulse/a (mac_1/mac/regs_int/short_impulse/a)
     INV:I->O              1   0.479   0.681  mac_1/mac/regs_int/short_impulse/a_not00011_INV_0 (mac_1/mac/regs_int/short_impulse/a_not0001)
     FDC:D                     0.176          mac_1/mac/regs_int/short_impulse/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy2RxClk'
  Clock period: 13.007ns (frequency: 76.879MHz)
  Total number of paths / destination ports: 9294 / 713
-------------------------------------------------------------------------
Delay:               13.007ns (Levels of Logic = 8)
  Source:            mac_2/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (FF)
  Destination:       mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr (FF)
  Source Clock:      Phy2RxClk rising
  Destination Clock: Phy2RxClk rising

  Data Path: mac_2/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 to mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.626   1.078  mac_2/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (mac_2/mac/mac_rx/mac_rx_ctrl/IFG_counter_4)
     LUT2:I0->O            1   0.479   0.851  mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002411 (mac_2/mac/mac_rx/mac_rx_ctrl/N9)
     LUT4:I1->O            1   0.479   0.976  mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289 (mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289)
     LUT4:I0->O            1   0.479   0.851  mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865 (mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865)
     LUT3:I1->O            2   0.479   1.040  mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq00028148 (mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002)
     LUT4:I0->O            2   0.479   0.804  mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_FSM_FFd12-In (mac_2/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0014)
     LUT4:I2->O            2   0.479   1.040  mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001292 (mac_2/mac/mac_rx/mac_rx_ctrl/N19)
     LUT3:I0->O            1   0.479   0.704  mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001_SW1 (N3800)
     LUT4:I3->O            1   0.479   0.681  mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001 (mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001)
     FDCE:CE                   0.524          mac_2/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
    ----------------------------------------
    Total                     13.007ns (4.982ns logic, 8.025ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_2/mac/mac_rx/mac_rx_ff/write/Packet_number_add'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Destination:       mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Source Clock:      mac_2/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising
  Destination Clock: mac_2/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising

  Data Path: mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg to mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)
     INV:I->O              1   0.479   0.681  mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not00011_INV_0 (mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not0001)
     FDC:D                     0.176          mac_2/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy2TxClk'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_2/mac/clock_ctrl/shorter/a (FF)
  Destination:       mac_2/mac/clock_ctrl/shorter/a (FF)
  Source Clock:      Phy2TxClk rising
  Destination Clock: Phy2TxClk rising

  Data Path: mac_2/mac/clock_ctrl/shorter/a to mac_2/mac/clock_ctrl/shorter/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_2/mac/clock_ctrl/shorter/a (mac_2/mac/clock_ctrl/shorter/a)
     INV:I->O              1   0.479   0.681  mac_2/mac/clock_ctrl/shorter/a_not00011_INV_0 (mac_2/mac/clock_ctrl/shorter/a_not0001)
     FDC:D                     0.176          mac_2/mac/clock_ctrl/shorter/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_2/mac/regs_int/RmonReadx'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_2/mac/regs_int/short_impulse/a (FF)
  Destination:       mac_2/mac/regs_int/short_impulse/a (FF)
  Source Clock:      mac_2/mac/regs_int/RmonReadx rising
  Destination Clock: mac_2/mac/regs_int/RmonReadx rising

  Data Path: mac_2/mac/regs_int/short_impulse/a to mac_2/mac/regs_int/short_impulse/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_2/mac/regs_int/short_impulse/a (mac_2/mac/regs_int/short_impulse/a)
     INV:I->O              1   0.479   0.681  mac_2/mac/regs_int/short_impulse/a_not00011_INV_0 (mac_2/mac/regs_int/short_impulse/a_not0001)
     FDC:D                     0.176          mac_2/mac/regs_int/short_impulse/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy3RxClk'
  Clock period: 13.007ns (frequency: 76.879MHz)
  Total number of paths / destination ports: 9294 / 713
-------------------------------------------------------------------------
Delay:               13.007ns (Levels of Logic = 8)
  Source:            mac_3/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (FF)
  Destination:       mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr (FF)
  Source Clock:      Phy3RxClk rising
  Destination Clock: Phy3RxClk rising

  Data Path: mac_3/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 to mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.626   1.078  mac_3/mac/mac_rx/mac_rx_ctrl/IFG_counter_4 (mac_3/mac/mac_rx/mac_rx_ctrl/IFG_counter_4)
     LUT2:I0->O            1   0.479   0.851  mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002411 (mac_3/mac/mac_rx/mac_rx_ctrl/N9)
     LUT4:I1->O            1   0.479   0.976  mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289 (mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq000289)
     LUT4:I0->O            1   0.479   0.851  mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865 (mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002865)
     LUT3:I1->O            2   0.479   1.040  mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq00028148 (mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0002)
     LUT4:I0->O            2   0.479   0.804  mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_FSM_FFd12-In (mac_3/mac/mac_rx/mac_rx_ctrl/Current_state_cmp_eq0014)
     LUT4:I2->O            2   0.479   1.040  mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001292 (mac_3/mac/mac_rx/mac_rx_ctrl/N19)
     LUT3:I0->O            1   0.479   0.704  mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001_SW1 (N3798)
     LUT4:I3->O            1   0.479   0.681  mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001 (mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr_not0001)
     FDCE:CE                   0.524          mac_3/mac/mac_rx/mac_rx_ctrl/broadcast_ptr
    ----------------------------------------
    Total                     13.007ns (4.982ns logic, 8.025ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_3/mac/mac_rx/mac_rx_ff/write/Packet_number_add'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Destination:       mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (FF)
  Source Clock:      mac_3/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising
  Destination Clock: mac_3/mac/mac_rx/mac_rx_ff/write/Packet_number_add rising

  Data Path: mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg to mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg (mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg)
     INV:I->O              1   0.479   0.681  mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not00011_INV_0 (mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg_not0001)
     FDC:D                     0.176          mac_3/mac/mac_rx/mac_rx_ff/Packet_number_add_reg
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Phy3TxClk'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_3/mac/clock_ctrl/shorter/a (FF)
  Destination:       mac_3/mac/clock_ctrl/shorter/a (FF)
  Source Clock:      Phy3TxClk rising
  Destination Clock: Phy3TxClk rising

  Data Path: mac_3/mac/clock_ctrl/shorter/a to mac_3/mac/clock_ctrl/shorter/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_3/mac/clock_ctrl/shorter/a (mac_3/mac/clock_ctrl/shorter/a)
     INV:I->O              1   0.479   0.681  mac_3/mac/clock_ctrl/shorter/a_not00011_INV_0 (mac_3/mac/clock_ctrl/shorter/a_not0001)
     FDC:D                     0.176          mac_3/mac/clock_ctrl/shorter/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mac_3/mac/regs_int/RmonReadx'
  Clock period: 2.707ns (frequency: 369.372MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               2.707ns (Levels of Logic = 1)
  Source:            mac_3/mac/regs_int/short_impulse/a (FF)
  Destination:       mac_3/mac/regs_int/short_impulse/a (FF)
  Source Clock:      mac_3/mac/regs_int/RmonReadx rising
  Destination Clock: mac_3/mac/regs_int/RmonReadx rising

  Data Path: mac_3/mac/regs_int/short_impulse/a to mac_3/mac/regs_int/short_impulse/a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.626   0.745  mac_3/mac/regs_int/short_impulse/a (mac_3/mac/regs_int/short_impulse/a)
     INV:I->O              1   0.479   0.681  mac_3/mac/regs_int/short_impulse/a_not00011_INV_0 (mac_3/mac/regs_int/short_impulse/a_not0001)
     FDC:D                     0.176          mac_3/mac/regs_int/short_impulse/a
    ----------------------------------------
    Total                      2.707ns (1.281ns logic, 1.426ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BusSpiSck'
  Total number of paths / destination ports: 123 / 105
-------------------------------------------------------------------------
Offset:              9.843ns (Levels of Logic = 14)
  Source:            Sfp1Test (PAD)
  Destination:       spi_to_epc/SpiMiso (FF)
  Destination Clock: BusSpiSck falling

  Data Path: Sfp1Test to spi_to_epc/SpiMiso
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.715   0.949  Sfp1Test_IBUF (Sfp1Test_IBUF)
     LUT3:I1->O            1   0.479   0.000  sfp/MuxBusDataRead_1_MuxBusDataRead<0>105_F (N4632)
     MUXF5:I0->O           1   0.314   0.704  sfp/MuxBusDataRead_1_MuxBusDataRead<0>105 (sfp/MuxBusDataRead_1_MuxBusDataRead<0>105)
     LUT4:I3->O            1   0.479   0.976  sfp/MuxBusDataRead_1_MuxBusDataRead<0>124_SW1 (N2565)
     LUT3:I0->O            1   0.479   0.000  sfp/MuxBusDataRead_1_MuxBusDataRead<0>150_SW0_G (N4595)
     MUXF5:I1->O           1   0.314   0.740  sfp/MuxBusDataRead_1_MuxBusDataRead<0>150_SW0 (N2465)
     LUT4:I2->O            1   0.479   0.000  spi_to_epc/Mmux__varindex0000_1613 (spi_to_epc/Mmux__varindex0000_1613)
     MUXF5:I0->O           1   0.314   0.000  spi_to_epc/Mmux__varindex0000_14_f5_10 (spi_to_epc/Mmux__varindex0000_14_f511)
     MUXF6:I1->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_13_f6_1 (spi_to_epc/Mmux__varindex0000_13_f62)
     MUXF7:I0->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_11_f7_1 (spi_to_epc/Mmux__varindex0000_11_f72)
     MUXF8:I0->O           1   0.298   0.740  spi_to_epc/Mmux__varindex0000_9_f8_1 (spi_to_epc/Mmux__varindex0000_9_f82)
     LUT3:I2->O            1   0.479   0.000  spi_to_epc/Mmux__varindex0000_6 (spi_to_epc/Mmux__varindex0000_6)
     MUXF5:I0->O           1   0.314   0.000  spi_to_epc/Mmux__varindex0000_4_f5 (spi_to_epc/Mmux__varindex0000_4_f5)
     MUXF6:I0->O           1   0.298   0.000  spi_to_epc/Mmux__varindex0000_2_f6 (spi_to_epc/_varindex0000)
     FDS_1:D                   0.176          spi_to_epc/SpiMiso
    ----------------------------------------
    Total                      9.843ns (5.734ns logic, 4.109ns route)
                                       (58.3% logic, 41.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BusRxClock_p'
  Total number of paths / destination ports: 784 / 225
-------------------------------------------------------------------------
Offset:              6.303ns (Levels of Logic = 34)
  Source:            BusTimeLoad (PAD)
  Destination:       timer/Second_31 (FF)
  Destination Clock: BusRxClock_p rising

  Data Path: BusTimeLoad to timer/Second_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            67   0.715   1.746  BusTimeLoad_IBUF (BusTimeLoad_IBUF)
     INV:I->O              1   0.479   0.681  timer/Load_inv1_INV_0 (timer/Load_inv)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<0> (timer/Mcount_Second_cy<0>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<1> (timer/Mcount_Second_cy<1>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<2> (timer/Mcount_Second_cy<2>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<3> (timer/Mcount_Second_cy<3>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<4> (timer/Mcount_Second_cy<4>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<5> (timer/Mcount_Second_cy<5>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<6> (timer/Mcount_Second_cy<6>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<7> (timer/Mcount_Second_cy<7>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<8> (timer/Mcount_Second_cy<8>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<9> (timer/Mcount_Second_cy<9>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<10> (timer/Mcount_Second_cy<10>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<11> (timer/Mcount_Second_cy<11>)
     MUXCY:CI->O           1   0.055   0.000  timer/Mcount_Second_cy<12> (timer/Mcount_Second_cy<12>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<13> (timer/Mcount_Second_cy<13>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<14> (timer/Mcount_Second_cy<14>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<15> (timer/Mcount_Second_cy<15>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<16> (timer/Mcount_Second_cy<16>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<17> (timer/Mcount_Second_cy<17>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<18> (timer/Mcount_Second_cy<18>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<19> (timer/Mcount_Second_cy<19>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<20> (timer/Mcount_Second_cy<20>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<21> (timer/Mcount_Second_cy<21>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<22> (timer/Mcount_Second_cy<22>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<23> (timer/Mcount_Second_cy<23>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<24> (timer/Mcount_Second_cy<24>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<25> (timer/Mcount_Second_cy<25>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<26> (timer/Mcount_Second_cy<26>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<27> (timer/Mcount_Second_cy<27>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<28> (timer/Mcount_Second_cy<28>)
     MUXCY:CI->O           1   0.056   0.000  timer/Mcount_Second_cy<29> (timer/Mcount_Second_cy<29>)
     MUXCY:CI->O           0   0.056   0.000  timer/Mcount_Second_cy<30> (timer/Mcount_Second_cy<30>)
     XORCY:CI->O           1   0.786   0.000  timer/Mcount_Second_xor<31> (timer/Mcount_Second31)
     FDCE:D                    0.176          timer/Second_31
    ----------------------------------------
    Total                      6.303ns (3.877ns logic, 2.426ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SramCq'
  Total number of paths / destination ports: 36 / 36
-------------------------------------------------------------------------
Offset:              0.891ns (Levels of Logic = 0)
  Source:            SramQ<0> (PAD)
  Destination:       sram/read[0].read/RD_FDC (UNKNOWN)
  Destination Clock: SramCq rising +-32

  Data Path: SramQ<0> to sram/read[0].read/RD_FDC
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IFDDRRSE:D                0.891          sram/read[0].read/RD_FDC
    ----------------------------------------
    Total                      0.891ns (0.891ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Phy0RxClk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            Phy0RxDv (PAD)
  Destination:       mac_0/mac/phy_int/Rx_dv_dl1 (FF)
  Destination Clock: Phy0RxClk rising

  Data Path: Phy0RxDv to mac_0/mac/phy_int/Rx_dv_dl1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  Phy0RxDv_IBUF (Phy0RxDv_IBUF)
     FDC:D                     0.176          mac_0/mac/phy_int/Rx_dv_dl1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Phy1RxClk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            Phy1RxDv (PAD)
  Destination:       mac_1/mac/phy_int/Rx_dv_dl1 (FF)
  Destination Clock: Phy1RxClk rising

  Data Path: Phy1RxDv to mac_1/mac/phy_int/Rx_dv_dl1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  Phy1RxDv_IBUF (Phy1RxDv_IBUF)
     FDC:D                     0.176          mac_1/mac/phy_int/Rx_dv_dl1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Phy2RxClk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            Phy2RxDv (PAD)
  Destination:       mac_2/mac/phy_int/Rx_dv_dl1 (FF)
  Destination Clock: Phy2RxClk rising

  Data Path: Phy2RxDv to mac_2/mac/phy_int/Rx_dv_dl1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  Phy2RxDv_IBUF (Phy2RxDv_IBUF)
     FDC:D                     0.176          mac_2/mac/phy_int/Rx_dv_dl1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Phy3RxClk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              1.572ns (Levels of Logic = 1)
  Source:            Phy3RxDv (PAD)
  Destination:       mac_3/mac/phy_int/Rx_dv_dl1 (FF)
  Destination Clock: Phy3RxClk rising

  Data Path: Phy3RxDv to mac_3/mac/phy_int/Rx_dv_dl1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.715   0.681  Phy3RxDv_IBUF (Phy3RxDv_IBUF)
     FDC:D                     0.176          mac_3/mac/phy_int/Rx_dv_dl1
    ----------------------------------------
    Total                      1.572ns (0.891ns logic, 0.681ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'spi_to_epc/Write'
  Total number of paths / destination ports: 108 / 39
-------------------------------------------------------------------------
Offset:              9.126ns (Levels of Logic = 3)
  Source:            sfp/Sfp1Mask (FF)
  Destination:       BusSfpIrq (PAD)
  Source Clock:      spi_to_epc/Write falling

  Data Path: sfp/Sfp1Mask to BusSfpIrq
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.626   0.976  sfp/Sfp1Mask (sfp/Sfp1Mask)
     LUT3:I0->O            1   0.479   0.976  sfp/SfpInterrupt2 (sfp/SfpInterrupt2)
     LUT4:I0->O            1   0.479   0.681  sfp/SfpInterrupt24 (BusSfpIrq_OBUF)
     OBUF:I->O                 4.909          BusSfpIrq_OBUF (BusSfpIrq)
    ----------------------------------------
    Total                      9.126ns (6.493ns logic, 2.633ns route)
                                       (71.2% logic, 28.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BusRxClock_p'
  Total number of paths / destination ports: 227 / 139
-------------------------------------------------------------------------
Offset:              9.001ns (Levels of Logic = 3)
  Source:            sfp/los/sfp1/TempIrq (FF)
  Destination:       BusSfpIrq (PAD)
  Source Clock:      BusRxClock_p rising

  Data Path: sfp/los/sfp1/TempIrq to BusSfpIrq
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.626   0.851  sfp/los/sfp1/TempIrq (sfp/los/sfp1/TempIrq)
     LUT3:I1->O            1   0.479   0.976  sfp/SfpInterrupt2 (sfp/SfpInterrupt2)
     LUT4:I0->O            1   0.479   0.681  sfp/SfpInterrupt24 (BusSfpIrq_OBUF)
     OBUF:I->O                 4.909          BusSfpIrq_OBUF (BusSfpIrq)
    ----------------------------------------
    Total                      9.001ns (6.493ns logic, 2.508ns route)
                                       (72.1% logic, 27.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BusSpiSck'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.216ns (Levels of Logic = 1)
  Source:            spi_to_epc/SpiMiso (FF)
  Destination:       BusSpiMiso (PAD)
  Source Clock:      BusSpiSck falling

  Data Path: spi_to_epc/SpiMiso to BusSpiMiso
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS_1:C->Q            1   0.626   0.681  spi_to_epc/SpiMiso (spi_to_epc/SpiMiso)
     OBUF:I->O                 4.909          BusSpiMiso_OBUF (BusSpiMiso)
    ----------------------------------------
    Total                      6.216ns (5.535ns logic, 0.681ns route)
                                       (89.0% logic, 11.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 81 / 23
-------------------------------------------------------------------------
Delay:               11.846ns (Levels of Logic = 4)
  Source:            BusRxClock_p (PAD)
  Destination:       Phy2GTxClk (PAD)

  Data Path: BusRxClock_p to Phy2GTxClk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUFDS:I->O           1   0.715   0.681  clock_gen/rx_clockx1 (clock_gen/BusClock125)
     BUFG:I->O          7070   0.357   4.024  clock_gen/bufgx1 (Clock125)
     LUT2:I1->O            1   0.479   0.681  mac_3/mac/clock_ctrl/GtxClock1 (Phy3GTxClk_OBUF)
     OBUF:I->O                 4.909          Phy3GTxClk_OBUF (Phy3GTxClk)
    ----------------------------------------
    Total                     11.846ns (6.460ns logic, 5.386ns route)
                                       (54.5% logic, 45.5% route)

=========================================================================


Total REAL time to Xst completion: 156.00 secs
Total CPU time to Xst completion: 156.14 secs
 
--> 

Total memory usage is 308128 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings : 1798 (   0 filtered)
Number of infos    :  175 (   0 filtered)