library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; entity fifo_tr is port ( --inputs signal clk : in std_logic; signal clk_tr : in std_logic; signal address : in std_logic; signal chipselect : in std_logic; signal write_n,read_n : in std_logic; signal writedata : in std_logic_vector(8 downto 1); --outputs --signal tr_read : out std_logic_vector(7 downto 0); --data for transmiter signal ff_out: out std_logic_vector(7 downto 0); signal irq : out std_logic; signal readdata : out std_logic_vector(8 downto 1); -- buffer signal rdusedw_d : buffer std_logic_vector(11 downto 0); signal wrusedw_d : buffer std_logic_vector(11 downto 0) ); end fifo_tr; architecture cosmos of fifo_tr is signal data_d : std_logic_vector(7 downto 0); signal wrfull_d : std_logic; signal rdfull_d : std_logic; signal wrempty_d : std_logic; signal rdempty_d : std_logic; signal rdreq_d : std_logic; signal wrreq_d : std_logic; signal flag_rd_end : std_logic; signal schetchik : std_logic_vector(11 downto 0) := "000000000000"; signal schetchik_2 : std_logic_vector(11 downto 0) := "000000000000"; signal dlina_kadra : std_logic_vector(11 downto 0) := "000000000000"; signal stat_reg : std_logic_vector(7 downto 0); -- статусный регистр: (0:2)бит - поле дынных содержит режим, устанавливающий размер видеостроки(размер пакета) -- 3 - фифо пустой -- 4 - фифо полный -- 5 - ошибка: превышение заданных размеров контейнера -- 6 - контейнер заполнен -- 7 - контейнер отправлен component dcfifo generic ( add_ram_output_register : string := "OFF"; add_usedw_msb_bit : string := "OFF"; clocks_are_synchronized : string := "FALSE"; delay_rdusedw : natural := 1; delay_wrusedw : natural := 1; intended_device_family : string := "unused"; lpm_numwords : natural; lpm_showahead : string := "OFF"; lpm_width : natural; lpm_widthu : natural := 1; overflow_checking : string := "ON"; rdsync_delaypipe : natural := 3; underflow_checking : string := "ON"; use_eab : string := "ON"; write_aclr_synch : string := "ON"; wrsync_delaypipe : natural := 3; lpm_hint : string := "USE_EAB=ON"; lpm_type : string := "dcfifo" ); port( aclr : in std_logic := '0'; data : in std_logic_vector(lpm_width-1 downto 0); q : out std_logic_vector(lpm_width-1 downto 0); rdclk : in std_logic; rdempty : out std_logic; rdfull : out std_logic; rdreq : in std_logic; rdusedw : out std_logic_vector(lpm_widthu - 1 downto 0); wrclk : in std_logic; wrempty : out std_logic; wrfull : out std_logic; wrreq : in std_logic; wrusedw : out std_logic_vector(lpm_widthu - 1 downto 0) ); end component; begin ff_tr1: dcfifo generic map(lpm_numwords => 4096, lpm_showahead => "ON", add_ram_output_register => "ON", delay_rdusedw => 0, delay_wrusedw => 0, rdsync_delaypipe => 3, wrsync_delaypipe => 3, lpm_width => 8, lpm_widthu => 12) port map( aclr => open, data => data_d, q => ff_out, rdclk => clk_tr, rdempty => rdempty_d, rdfull => rdfull_d, rdreq => rdreq_d, rdusedw => rdusedw_d, wrclk => clk, wrempty => wrempty_d, wrfull => wrfull_d, wrreq => wrreq_d, wrusedw => wrusedw_d); -- процесс записи данных в фифо process(clk, chipselect, address, write_n) begin if clk = '1' and clk'event then if chipselect = '1' and write_n = '0' then if address = '0'then if (schetchik(11 downto 0) <= dlina_kadra(11 downto 0)) then data_d(7 downto 0) <= writedata(8 downto 1); -- запись данных wrreq_d <= '1'; schetchik <= schetchik + '1'; --aclr_d <= '1'; else --если количество байт превысило допустимые рзмеры кадра wrreq_d <= '0'; stat_reg(5) <= '1'; -- выставляем статус ошибка end if; elsif address = '1' then stat_reg(7 downto 0) <= writedata(8 downto 1); -- записываем в статусный регистр признак case writedata(3 downto 1) is -- сравнение значения статуса для выбора длинны строки when "001" => dlina_kadra(11 downto 0) <= "001100100000"; -- 800 when "010" => dlina_kadra(11 downto 0) <= "010000000000"; -- 1024 when "011" => dlina_kadra(11 downto 0) <= "010000011010"; -- 1050 when "100" => dlina_kadra(11 downto 0) <= "010100000000"; -- 1280 when "101" => dlina_kadra(11 downto 0) <= "010101111000"; -- 1400 when "110" => dlina_kadra(11 downto 0) <= "011010010000"; -- 1680 when "111" => dlina_kadra(11 downto 0) <= "100000000000"; -- 2048 when others => dlina_kadra(11 downto 0) <= "000000001010"; -- в целях отладки end case; wrreq_d <= '0'; end if; elsif chipselect = '1' and read_n = '0' then if address = '0' then readdata(8 downto 1) <= data_d(7 downto 0); wrreq_d <= '0'; elsif address = '1' then readdata(8 downto 1) <= stat_reg(7 downto 0); wrreq_d <= '0'; end if; else wrreq_d <= '0'; end if; if chipselect = '0' and (schetchik(11 downto 0) <= dlina_kadra(11 downto 0)) and (schetchik(11 downto 0) > "000000000000") then stat_reg(6) <= '1'; --aclr_d <= '0'; elsif chipselect = '0'and (schetchik(11 downto 0) = "000000000000") then irq <= '1'; elsif chipselect = '1' then irq <= '0'; end if; if (flag_rd_end = '1') then schetchik(11 downto 0) <= "000000000000"; stat_reg(6) <= '0'; stat_reg(7) <= '1'; wrreq_d <= '0'; end if; stat_reg(3) <= rdempty_d; stat_reg(4) <= wrfull_d; end if; end process; process(clk_tr, chipselect, stat_reg) begin if clk_tr = '0' and clk_tr'event then if chipselect = '0' and stat_reg(6) = '1' then if (schetchik_2(11 downto 0) <= schetchik(11 downto 0)) then rdreq_d <= '1'; schetchik_2 <= schetchik_2 + '1'; flag_rd_end <= '0'; else flag_rd_end <= '1'; schetchik_2 <= "000000000000"; rdreq_d <= '0'; end if; else rdreq_d <= '0'; end if; end if; end process; end architecture cosmos;