Warning (10036): Verilog HDL or VHDL warning at fifo_tr.vhd(35): object "rdfull_d" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at fifo_tr.vhd(36): object "wrempty_d" assigned a value but never read
Warning (14130): Reduced register "dlina_kadra[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "dlina_kadra[2]" with stuck data_in port to stuck value GND
Warning: No exact pin location assignment(s) for 55 pins of 55 total pins
Warning: Found pins functioning as undefined clocks and/or memory enables
	Info: Assuming node "clk_tr" is an undefined clock
	Info: Assuming node "clk" is an undefined clock
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo_tr -c fifo_tr
Info: Found 2 design units, including 1 entities, in source file fifo_tr.vhd
Info: Elaborating entity "fifo_tr" for the top level hierarchy
Info: Elaborating entity "dcfifo" for hierarchy "dcfifo:ff_tr1"
Info: Elaborated megafunction instantiation "dcfifo:ff_tr1"
Info: Instantiated megafunction "dcfifo:ff_tr1" with the following parameter:
	Info: Parameter "add_ram_output_register" = "ON"
	Info: Parameter "add_usedw_msb_bit" = "OFF"
	Info: Parameter "clocks_are_synchronized" = "FALSE"
	Info: Parameter "delay_rdusedw" = "0"
	Info: Parameter "delay_wrusedw" = "0"
	Info: Parameter "intended_device_family" = "unused"
	Info: Parameter "lpm_numwords" = "4096"
	Info: Parameter "lpm_showahead" = "ON"
	Info: Parameter "lpm_width" = "8"
	Info: Parameter "lpm_widthu" = "12"
	Info: Parameter "overflow_checking" = "ON"
	Info: Parameter "rdsync_delaypipe" = "3"
	Info: Parameter "underflow_checking" = "ON"
	Info: Parameter "use_eab" = "ON"
	Info: Parameter "write_aclr_synch" = "ON"
	Info: Parameter "wrsync_delaypipe" = "3"
	Info: Parameter "lpm_hint" = "USE_EAB=ON"
	Info: Parameter "lpm_type" = "dcfifo"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_vbs1.tdf
	Info: Found entity 1: dcfifo_vbs1
Info: Elaborating entity "dcfifo_vbs1" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_46b.tdf
	Info: Found entity 1: a_gray2bin_46b
Info: Elaborating entity "a_gray2bin_46b" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|a_gray2bin_46b:read_side_gray_converter"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_t16.tdf
	Info: Found entity 1: a_graycounter_t16
Info: Elaborating entity "a_graycounter_t16" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|a_graycounter_t16:rdptr_g"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_426.tdf
	Info: Found entity 1: a_graycounter_426
Info: Elaborating entity "a_graycounter_426" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|a_graycounter_426:read_counter_for_write"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8941.tdf
	Info: Found entity 1: altsyncram_8941
Info: Elaborating entity "altsyncram_8941" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|altsyncram_8941:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ue8.tdf
	Info: Found entity 1: alt_synch_pipe_ue8
Info: Elaborating entity "alt_synch_pipe_ue8" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ue8:read_sync_registers"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pf9.tdf
	Info: Found entity 1: dffpipe_pf9
Info: Elaborating entity "dffpipe_pf9" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ue8:read_sync_registers|dffpipe_pf9:dffpipe11"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ve8.tdf
	Info: Found entity 1: alt_synch_pipe_ve8
Info: Elaborating entity "alt_synch_pipe_ve8" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qf9.tdf
	Info: Found entity 1: dffpipe_qf9
Info: Elaborating entity "dffpipe_qf9" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_qvb.tdf
	Info: Found entity 1: add_sub_qvb
Info: Elaborating entity "add_sub_qvb" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor"
Info: Found 1 design units, including 1 entities, in source file db/cntr_bua.tdf
	Info: Found entity 1: cntr_bua
Info: Elaborating entity "cntr_bua" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|cntr_bua:rdptr_b"
Info: Elaborating entity "scfifo" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel"
Info: Elaborated megafunction instantiation "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel"
Info: Instantiated megafunction "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel" with the following parameter:
	Info: Parameter "ADD_RAM_OUTPUT_REGISTER" = "ON"
	Info: Parameter "LPM_NUMWORDS" = "3"
	Info: Parameter "LPM_SHOWAHEAD" = "ON"
	Info: Parameter "lpm_width" = "8"
	Info: Parameter "lpm_widthu" = "2"
	Info: Parameter "OVERFLOW_CHECKING" = "ON"
	Info: Parameter "UNDERFLOW_CHECKING" = "ON"
	Info: Parameter "USE_EAB" = "OFF"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_kb11.tdf
	Info: Found entity 1: scfifo_kb11
Info: Elaborating entity "scfifo_kb11" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_rh11.tdf
	Info: Found entity 1: a_dpfifo_rh11
Info: Elaborating entity "a_dpfifo_rh11" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lha1.tdf
	Info: Found entity 1: altsyncram_lha1
Info: Elaborating entity "altsyncram_lha1" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|altsyncram_lha1:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cntr_obb.tdf
	Info: Found entity 1: cntr_obb
Info: Elaborating entity "cntr_obb" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|cntr_obb:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_5c7.tdf
	Info: Found entity 1: cntr_5c7
Info: Elaborating entity "cntr_5c7" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|cntr_5c7:usedw_counter"
Info: Found 1 design units, including 1 entities, in source file db/cntr_pbb.tdf
	Info: Found entity 1: cntr_pbb
Info: Elaborating entity "cntr_pbb" for hierarchy "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|cntr_pbb:wr_ptr"
Info: Implemented 448 device resources after synthesis - the final resource count might be different
	Info: Implemented 14 input pins
	Info: Implemented 41 output pins
	Info: Implemented 377 logic cells
	Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
	Info: Peak virtual memory: 186 megabytes
	Info: Processing ended: Tue Oct 27 09:49:05 2009
	Info: Elapsed time: 00:00:04
	Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Fitter
	Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
	Info: Processing started: Tue Oct 27 09:49:06 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off fifo_tr -c fifo_tr
Info: Selected device EP1C12Q240I7 for design "fifo_tr"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
	Info: Device EP1C6Q240C7 is compatible
	Info: Device EP1C6Q240I7 is compatible
	Info: Device EP1C12Q240C7 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
	Info: Pin ~nCSO~ is reserved at location 24
	Info: Pin ~ASDO~ is reserved at location 37
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 29
Info: Automatically promoted signal "clk_tr" to use Global clock in PIN 28
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
	Info: Number of I/O pins in group: 53 (unused VREF, 3.3V VCCIO, 12 input, 41 output, 0 bidirectional)
		Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
	Info: Statistics of I/O banks
		Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  40 pins available
		Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available
		Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  45 pins available
		Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 4.431 ns
	Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y15; Fanout = 2; REG Node = 'rdreq_d'
	Info: 2: + IC(0.123 ns) + CELL(0.522 ns) = 0.645 ns; Loc. = LAB_X28_Y15; Fanout = 33; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|valid_rreq'
	Info: 3: + IC(1.112 ns) + CELL(0.101 ns) = 1.858 ns; Loc. = LAB_X28_Y12; Fanout = 1; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|_~51'
	Info: 4: + IC(0.823 ns) + CELL(0.390 ns) = 3.071 ns; Loc. = LAB_X28_Y15; Fanout = 1; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|wait_state~0'
	Info: 5: + IC(0.823 ns) + CELL(0.537 ns) = 4.431 ns; Loc. = LAB_X29_Y12; Fanout = 3; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|empty_dff'
	Info: Total cell delay = 1.550 ns ( 34.98 % )
	Info: Total interconnect delay = 2.881 ns ( 65.02 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources
	Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y0 to location X31_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
	Info: Optimizations that may affect the design's routability were skipped
	Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Generated suppressed messages file D:/Projects/altera/F_tr_8/fifo_tr.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 1 warning
	Info: Peak virtual memory: 189 megabytes
	Info: Processing ended: Tue Oct 27 09:49:12 2009
	Info: Elapsed time: 00:00:06
	Info: Total CPU time (on all processors): 00:00:06
Info: *******************************************************************
Info: Running Quartus II Assembler
	Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
	Info: Processing started: Tue Oct 27 09:49:13 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off fifo_tr -c fifo_tr
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
	Info: Peak virtual memory: 148 megabytes
	Info: Processing ended: Tue Oct 27 09:49:14 2009
	Info: Elapsed time: 00:00:01
	Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
	Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
	Info: Processing started: Tue Oct 27 09:49:15 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fifo_tr -c fifo_tr --timing_analysis_only
Info: Slack time is 3.619 ns for clock "clk_tr" between source register "rdreq_d" and destination register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|empty_dff"
	Info: Fmax is 78.36 MHz (period= 12.762 ns)
	Info: + Largest register to register requirement is 9.710 ns
		Info: + Setup relationship between source and destination is 10.000 ns
			Info: + Latch edge is 20.000 ns
				Info: Clock period of Destination clock "clk_tr" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Destination register is 1
			Info: - Launch edge is 10.000 ns
				Info: Clock period of Source clock "clk_tr" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Source register is 1
		Info: + Largest clock skew is -0.059 ns
			Info: + Shortest clock path from clock "clk_tr" to destination register is 2.749 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 250; CLK Node = 'clk_tr'
				Info: 2: + IC(0.821 ns) + CELL(0.629 ns) = 2.749 ns; Loc. = LC_X29_Y12_N3; Fanout = 3; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|empty_dff'
				Info: Total cell delay = 1.928 ns ( 70.13 % )
				Info: Total interconnect delay = 0.821 ns ( 29.87 % )
			Info: - Longest clock path from clock "clk_tr" to source register is 2.808 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 250; CLK Node = 'clk_tr'
				Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X28_Y15_N5; Fanout = 2; REG Node = 'rdreq_d'
				Info: Total cell delay = 1.928 ns ( 68.66 % )
				Info: Total interconnect delay = 0.880 ns ( 31.34 % )
		Info: - Micro clock to output delay of source is 0.198 ns
		Info: - Micro setup delay of destination is 0.033 ns
	Info: - Longest register to register delay is 6.091 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y15_N5; Fanout = 2; REG Node = 'rdreq_d'
		Info: 2: + IC(0.473 ns) + CELL(0.390 ns) = 0.863 ns; Loc. = LC_X28_Y15_N1; Fanout = 33; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|valid_rreq'
		Info: 3: + IC(1.169 ns) + CELL(0.522 ns) = 2.554 ns; Loc. = LC_X28_Y12_N3; Fanout = 1; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|_~51'
		Info: 4: + IC(1.760 ns) + CELL(0.258 ns) = 4.572 ns; Loc. = LC_X28_Y15_N9; Fanout = 1; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|wait_state~0'
		Info: 5: + IC(1.096 ns) + CELL(0.423 ns) = 6.091 ns; Loc. = LC_X29_Y12_N3; Fanout = 3; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|empty_dff'
		Info: Total cell delay = 1.593 ns ( 26.15 % )
		Info: Total interconnect delay = 4.498 ns ( 73.85 % )
Info: Slack time is 13.494 ns for clock "clk" between source register "schetchik[2]" and destination register "stat_reg[5]"
	Info: Fmax is 153.7 MHz (period= 6.506 ns)
	Info: + Largest register to register requirement is 19.800 ns
		Info: + Setup relationship between source and destination is 20.000 ns
			Info: + Latch edge is 20.000 ns
				Info: Clock period of Destination clock "clk" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Destination register is 1
			Info: - Launch edge is 0.000 ns
				Info: Clock period of Source clock "clk" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Source register is 1
		Info: + Largest clock skew is 0.031 ns
			Info: + Shortest clock path from clock "clk" to destination register is 2.869 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
				Info: 2: + IC(0.941 ns) + CELL(0.629 ns) = 2.869 ns; Loc. = LC_X21_Y16_N8; Fanout = 2; REG Node = 'stat_reg[5]'
				Info: Total cell delay = 1.928 ns ( 67.20 % )
				Info: Total interconnect delay = 0.941 ns ( 32.80 % )
			Info: - Longest clock path from clock "clk" to source register is 2.838 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
				Info: 2: + IC(0.910 ns) + CELL(0.629 ns) = 2.838 ns; Loc. = LC_X22_Y14_N6; Fanout = 7; REG Node = 'schetchik[2]'
				Info: Total cell delay = 1.928 ns ( 67.94 % )
				Info: Total interconnect delay = 0.910 ns ( 32.06 % )
		Info: - Micro clock to output delay of source is 0.198 ns
		Info: - Micro setup delay of destination is 0.033 ns
	Info: - Longest register to register delay is 6.306 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y14_N6; Fanout = 7; REG Node = 'schetchik[2]'
		Info: 2: + IC(0.495 ns) + CELL(0.522 ns) = 1.017 ns; Loc. = LC_X22_Y14_N1; Fanout = 2; COMB Node = 'LessThan0~265'
		Info: 3: + IC(0.624 ns) + CELL(0.499 ns) = 2.140 ns; Loc. = LC_X23_Y14_N0; Fanout = 1; COMB Node = 'LessThan0~266COUT0'
		Info: 4: + IC(0.000 ns) + CELL(0.069 ns) = 2.209 ns; Loc. = LC_X23_Y14_N1; Fanout = 1; COMB Node = 'LessThan0~262'
		Info: 5: + IC(0.000 ns) + CELL(0.069 ns) = 2.278 ns; Loc. = LC_X23_Y14_N2; Fanout = 1; COMB Node = 'LessThan0~257'
		Info: 6: + IC(0.000 ns) + CELL(0.069 ns) = 2.347 ns; Loc. = LC_X23_Y14_N3; Fanout = 1; COMB Node = 'LessThan0~252'
		Info: 7: + IC(0.000 ns) + CELL(0.157 ns) = 2.504 ns; Loc. = LC_X23_Y14_N4; Fanout = 1; COMB Node = 'LessThan0~247'
		Info: 8: + IC(0.000 ns) + CELL(0.549 ns) = 3.053 ns; Loc. = LC_X23_Y14_N9; Fanout = 6; COMB Node = 'LessThan0~220'
		Info: 9: + IC(1.441 ns) + CELL(0.101 ns) = 4.595 ns; Loc. = LC_X21_Y15_N8; Fanout = 1; COMB Node = 'stat_reg[5]~320'
		Info: 10: + IC(1.058 ns) + CELL(0.653 ns) = 6.306 ns; Loc. = LC_X21_Y16_N8; Fanout = 2; REG Node = 'stat_reg[5]'
		Info: Total cell delay = 2.688 ns ( 42.63 % )
		Info: Total interconnect delay = 3.618 ns ( 57.37 % )
Info: Minimum slack time is 727 ps for clock "clk_tr" between source register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]" and destination register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]"
	Info: + Shortest register to register delay is 0.542 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y15_N7; Fanout = 2; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]'
		Info: 2: + IC(0.000 ns) + CELL(0.542 ns) = 0.542 ns; Loc. = LC_X28_Y15_N7; Fanout = 2; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]'
		Info: Total cell delay = 0.542 ns ( 100.00 % )
	Info: - Smallest register to register requirement is -0.185 ns
		Info: + Hold relationship between source and destination is 0.000 ns
			Info: + Latch edge is 0.000 ns
				Info: Clock period of Destination clock "clk_tr" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Destination register is 1
				Info: Multicycle Hold factor for Destination register is 1
			Info: - Launch edge is 0.000 ns
				Info: Clock period of Source clock "clk_tr" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Source register is 1
				Info: Multicycle Hold factor for Source register is 1
		Info: + Smallest clock skew is 0.000 ns
			Info: + Longest clock path from clock "clk_tr" to destination register is 2.808 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 250; CLK Node = 'clk_tr'
				Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X28_Y15_N7; Fanout = 2; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]'
				Info: Total cell delay = 1.928 ns ( 68.66 % )
				Info: Total interconnect delay = 0.880 ns ( 31.34 % )
			Info: - Shortest clock path from clock "clk_tr" to source register is 2.808 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 250; CLK Node = 'clk_tr'
				Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X28_Y15_N7; Fanout = 2; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|scfifo:output_channel|scfifo_kb11:auto_generated|a_dpfifo_rh11:dpfifo|low_addressa[1]'
				Info: Total cell delay = 1.928 ns ( 68.66 % )
				Info: Total interconnect delay = 0.880 ns ( 31.34 % )
		Info: - Micro clock to output delay of source is 0.198 ns
		Info: + Micro hold delay of destination is 0.013 ns
Info: Minimum slack time is 762 ps for clock "clk" between source register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe17a[11]" and destination register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe18a[11]"
	Info: + Shortest register to register delay is 0.577 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y13_N8; Fanout = 1; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe17a[11]'
		Info: 2: + IC(0.475 ns) + CELL(0.102 ns) = 0.577 ns; Loc. = LC_X30_Y13_N9; Fanout = 4; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe18a[11]'
		Info: Total cell delay = 0.102 ns ( 17.68 % )
		Info: Total interconnect delay = 0.475 ns ( 82.32 % )
	Info: - Smallest register to register requirement is -0.185 ns
		Info: + Hold relationship between source and destination is 0.000 ns
			Info: + Latch edge is 0.000 ns
				Info: Clock period of Destination clock "clk" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Destination register is 1
				Info: Multicycle Hold factor for Destination register is 1
			Info: - Launch edge is 0.000 ns
				Info: Clock period of Source clock "clk" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50
				Info: Multicycle Setup factor for Source register is 1
				Info: Multicycle Hold factor for Source register is 1
		Info: + Smallest clock skew is 0.000 ns
			Info: + Longest clock path from clock "clk" to destination register is 2.808 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
				Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X30_Y13_N9; Fanout = 4; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe18a[11]'
				Info: Total cell delay = 1.928 ns ( 68.66 % )
				Info: Total interconnect delay = 0.880 ns ( 31.34 % )
			Info: - Shortest clock path from clock "clk" to source register is 2.808 ns
				Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
				Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X30_Y13_N8; Fanout = 1; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|alt_synch_pipe_ve8:write_sync_registers|dffpipe_qf9:dffpipe15|dffe17a[11]'
				Info: Total cell delay = 1.928 ns ( 68.66 % )
				Info: Total interconnect delay = 0.880 ns ( 31.34 % )
		Info: - Micro clock to output delay of source is 0.198 ns
		Info: + Micro hold delay of destination is 0.013 ns
Info: tsu for register "schetchik[0]" (data pin = "write_n", clock pin = "clk") is 7.272 ns
	Info: + Longest pin to register delay is 10.077 ns
		Info: 1: + IC(0.000 ns) + CELL(1.305 ns) = 1.305 ns; Loc. = PIN_214; Fanout = 6; PIN Node = 'write_n'
		Info: 2: + IC(6.379 ns) + CELL(0.522 ns) = 8.206 ns; Loc. = LC_X22_Y13_N6; Fanout = 12; COMB Node = 'schetchik[2]~380'
		Info: 3: + IC(1.104 ns) + CELL(0.767 ns) = 10.077 ns; Loc. = LC_X22_Y14_N4; Fanout = 5; REG Node = 'schetchik[0]'
		Info: Total cell delay = 2.594 ns ( 25.74 % )
		Info: Total interconnect delay = 7.483 ns ( 74.26 % )
	Info: + Micro setup delay of destination is 0.033 ns
	Info: - Shortest clock path from clock "clk" to destination register is 2.838 ns
		Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
		Info: 2: + IC(0.910 ns) + CELL(0.629 ns) = 2.838 ns; Loc. = LC_X22_Y14_N4; Fanout = 5; REG Node = 'schetchik[0]'
		Info: Total cell delay = 1.928 ns ( 67.94 % )
		Info: Total interconnect delay = 0.910 ns ( 32.06 % )
Info: tco from clock "clk_tr" to destination pin "rdusedw_d[6]" through register "dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|dffe7a[2]" is 11.671 ns
	Info: + Longest clock path from clock "clk_tr" to source register is 2.808 ns
		Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_28; Fanout = 250; CLK Node = 'clk_tr'
		Info: 2: + IC(0.880 ns) + CELL(0.629 ns) = 2.808 ns; Loc. = LC_X27_Y13_N2; Fanout = 3; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|dffe7a[2]'
		Info: Total cell delay = 1.928 ns ( 68.66 % )
		Info: Total interconnect delay = 0.880 ns ( 31.34 % )
	Info: + Micro clock to output delay of source is 0.198 ns
	Info: + Longest register to pin delay is 8.665 ns
		Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y13_N2; Fanout = 3; REG Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|dffe7a[2]'
		Info: 2: + IC(1.438 ns) + CELL(0.509 ns) = 1.947 ns; Loc. = LC_X28_Y14_N6; Fanout = 2; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor|add_sub_cella[0]~277COUT1'
		Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 2.018 ns; Loc. = LC_X28_Y14_N7; Fanout = 2; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor|add_sub_cella[0]~279COUT1'
		Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 2.089 ns; Loc. = LC_X28_Y14_N8; Fanout = 2; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor|add_sub_cella[0]~281COUT1'
		Info: 5: + IC(0.000 ns) + CELL(0.228 ns) = 2.317 ns; Loc. = LC_X28_Y14_N9; Fanout = 6; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor|add_sub_cella[0]~283'
		Info: 6: + IC(0.000 ns) + CELL(0.601 ns) = 2.918 ns; Loc. = LC_X28_Y13_N0; Fanout = 1; COMB Node = 'dcfifo:ff_tr1|dcfifo_vbs1:auto_generated|add_sub_qvb:rdusedw_subtractor|add_sub_cella[0]~284'
		Info: 7: + IC(3.882 ns) + CELL(1.865 ns) = 8.665 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'rdusedw_d[6]'
		Info: Total cell delay = 3.345 ns ( 38.60 % )
		Info: Total interconnect delay = 5.320 ns ( 61.40 % )
Info: th for register "data_d[7]" (data pin = "writedata[8]", clock pin = "clk") is -4.384 ns
	Info: + Longest clock path from clock "clk" to destination register is 2.838 ns
		Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_29; Fanout = 266; CLK Node = 'clk'
		Info: 2: + IC(0.910 ns) + CELL(0.629 ns) = 2.838 ns; Loc. = LC_X21_Y15_N1; Fanout = 2; REG Node = 'data_d[7]'
		Info: Total cell delay = 1.928 ns ( 67.94 % )
		Info: Total interconnect delay = 0.910 ns ( 32.06 % )
	Info: + Micro hold delay of destination is 0.013 ns
	Info: - Shortest pin to register delay is 7.235 ns
		Info: 1: + IC(0.000 ns) + CELL(1.305 ns) = 1.305 ns; Loc. = PIN_216; Fanout = 2; PIN Node = 'writedata[8]'
		Info: 2: + IC(5.657 ns) + CELL(0.273 ns) = 7.235 ns; Loc. = LC_X21_Y15_N1; Fanout = 2; REG Node = 'data_d[7]'
		Info: Total cell delay = 1.578 ns ( 21.81 % )
		Info: Total interconnect delay = 5.657 ns ( 78.19 % )
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
	Info: Peak virtual memory: 124 megabytes
	Info: Processing ended: Tue Oct 27 09:49:16 2009
	Info: Elapsed time: 00:00:01
	Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 7 warnings