run -all
# [ 0 ns ] : CoreName = pcie_endpoint_v1_11_pcie_blk_plus_gen_1
# [ 0 ns ] : #MSG: Running user_test0
# [ 3538.1 ns ] : Transaction Reset is De-asserted
# [ 69698.1 ns ] : Transaction Link is Up
# [ 69698.1 ns ] : PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN..
# Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR1
# Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR6
#             BAR 0 = 0x10000000 RANGE = 0xFFFE0000 MEM32 MAPPED
#             BAR 1 = 0x20000000 RANGE = 0xFFF80000 DISABLED
#             BAR 2 = 0x30000000 RANGE = 0xFFFFFF81 IO MAPPED
#             BAR 3 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 4 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 5 = 0x00000000 RANGE = 0x00000000 DISABLED
#             BAR 6 = 0x70000001 RANGE = 0xFFF00001 DISABLED
# [ 69698.1 ns ] : Setting Core Configuration Space...
# [ 69794 ns ] : PROC_PARSE_FRAME on Transmit
# [ 73026 ns ] : PROC_PARSE_FRAME on Receive
# [ 73090 ns ] : PROC_PARSE_FRAME on Transmit
# [ 75714 ns ] : PROC_PARSE_FRAME on Receive
# [ 76386 ns ] : PROC_PARSE_FRAME on Transmit
# [ 79042 ns ] : PROC_PARSE_FRAME on Receive
# [ 79682 ns ] : PROC_PARSE_FRAME on Transmit
# [ 82306 ns ] : PROC_PARSE_FRAME on Receive
# [ 82978 ns ] : PROC_PARSE_FRAME on Transmit
# [ 85602 ns ] : PROC_PARSE_FRAME on Receive
# [ 86274 ns ] : PROC_PARSE_FRAME on Transmit
# [ 88898 ns ] : PROC_PARSE_FRAME on Receive
# [ 89570 ns ] : PROC_PARSE_FRAME on Transmit
# [ 92226 ns ] : PROC_PARSE_FRAME on Receive
# [ 92866 ns ] : PROC_PARSE_FRAME on Transmit
# [ 95490 ns ] : PROC_PARSE_FRAME on Receive
# [ 96162 ns ] : PROC_PARSE_FRAME on Transmit
# [ 98786 ns ] : PROC_PARSE_FRAME on Receive
# [ 137762 ns ] : #MSG: Checking BAR0..
# [ 137762 ns ] : #MSG: Found Mem32 BAR0.
# [ 137762 ns ] : #MSG: Part I: Write - Read Back Test (32DW).
#MSG: Address Offset = 0x10000000".
# [ 137858 ns ] : PROC_PARSE_FRAME on Transmit
# [ 137954 ns ] : PROC_PARSE_FRAME on Transmit
# ** Note: Block Memory Generator CORE Generator module is using a behavioral model for simulation which will not precisely model memory collision behavior.
#    Time: 139202100 ps  Iteration: 9  Instance: /pcie_tb1/i_sram/u0
# [ 140706 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x04030201
#MSG: Address Offset = 0x10000004".
# [ 140898 ns ] : PROC_PARSE_FRAME on Transmit
# [ 140994 ns ] : PROC_PARSE_FRAME on Transmit
# [ 143714 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x08070605
#MSG: Address Offset = 0x10000008".
# [ 143906 ns ] : PROC_PARSE_FRAME on Transmit
# [ 144002 ns ] : PROC_PARSE_FRAME on Transmit
# [ 146722 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x0C0B0A09
#MSG: Address Offset = 0x1000000C".
# [ 146914 ns ] : PROC_PARSE_FRAME on Transmit
# [ 147010 ns ] : PROC_PARSE_FRAME on Transmit
# [ 149730 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x100F0E0D
#MSG: Address Offset = 0x10000010".
# [ 149922 ns ] : PROC_PARSE_FRAME on Transmit
# [ 150018 ns ] : PROC_PARSE_FRAME on Transmit
# [ 152738 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x14131211
#MSG: Address Offset = 0x10000014".
# [ 152930 ns ] : PROC_PARSE_FRAME on Transmit
# [ 153026 ns ] : PROC_PARSE_FRAME on Transmit
# [ 155746 ns ] : PROC_PARSE_FRAME on Receive
#MSG: Passed. Completion Data = 0x18171615
#MSG: Address Offset = 0x10000018".
# [ 155938 ns ] : PROC_PARSE_FRAME on Transmit
# [ 156034 ns ] : PROC_PARSE_FRAME on Transmit
# ** Failure: RX Simulation Timeout.
#    Time: 389730 ns  Iteration: 4  Process: /pcie_tb1/i_dsport/rx_app/line__816 File: D:/Projects/NIC/Xilinx/pcie_endpoint_v1_11/simulation/dsport/pci_exp_usrapp_rx.vhd
# Break in Process line__816 at D:/Projects/NIC/Xilinx/pcie_endpoint_v1_11/simulation/dsport/pci_exp_usrapp_rx.vhd line 830