/////////////////////////////////////////////////////////////// // // real endpoints' configuration // /////////////////////////////////////////////////////////////// //SLCS# and INT0 PORTACFG = 0x41; REVCTL = 0x03; // REVCTL.0 and REVCTL.1 set to 1 SYNCDELAY; EP1OUTCFG = (EP1OUTCFG & 0x7F);// EP1 is disabled SYNCDELAY; EP1INCFG = (EP1INCFG & 0x7F);// EP1 is disabled SYNCDELAY; //2 EP2CFG = 0xBA;// EP2 is DIR=OUT, TYPE=INT, SIZE=1024, BUF=2x SYNCDELAY; FIFORESET = 0x80; // Reset the FIFO SYNCDELAY; FIFORESET = 0x02; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; OUTPKTEND = 0x82; // Arm both EP2 buffers to “prime the pump” SYNCDELAY; OUTPKTEND = 0x82; SYNCDELAY; EP2FIFOCFG = 0x10; //AutoOut = 1, AutoIn = 0, 8bit SYNCDELAY; EP4CFG = (EP4CFG & 0x7F);// EP4 is disabled SYNCDELAY; EP4FIFOCFG = 0x00; //8bit for not WORDWIDE SYNCDELAY; EP8CFG = (EP8CFG & 0x7F);// EP8 is disabled SYNCDELAY; EP8FIFOCFG = 0x00; //8bit for not WORDWIDE SYNCDELAY; //6 EP6CFG = 0xFA;// EP6 is DIR=IN, TYPE=INT, SIZE=1024, BUF=2x SYNCDELAY; FIFORESET = 0x80; // Reset the FIFO SYNCDELAY; FIFORESET = 0x06; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; EP6FIFOCFG = 0x08; //AutoOut = 0, AutoIn = 1, 8bit SYNCDELAY; //IFCLKSRC-int 3048MHZ-48 IFCLKOE-en IFCLKPOL-pos ASYNC-no GSTATE-no IFCFG1-slave IFCFG0-slave // 1 1 1 0 0 0 1 1 //IFCONFIG = 0xE3; //48MHz IFCLK ASYNC-no IFCONFIG = 0xEB; //48MHz IFCLK ASYNC-yes //IFCONFIG = 0xAB; //30MHz IFCLK ASYNC-yes SYNCDELAY; FIFORESET = 0x80; // reset all FIFOs SYNCDELAY; FIFORESET = 0x04; SYNCDELAY; FIFORESET = 0x08; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; PINFLAGSAB = 0xE8;// defines FLAGA as EP2 EF and FLAGB as EP6 FF PINFLAGSCD = 0x00; // FLAGC as empty flag, EP is pointed by FIFOADR[1:0] // won't generally need FLAGD (EP2 PF) SYNCDELAY; FIFOPINPOLAR = 0x03; // set all slave FIFO interface pins as active low, but EF and FF active high SYNCDELAY; EP6AUTOINLENH = 0x04; // EZ-USB automatically commits data in 1024-byte chunks SYNCDELAY; EP6AUTOINLENL = 0x00; //end of real endpoints' configuration