Release 10.1.03 par K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. PC1:: Thu Feb 05 09:47:38 2009 par -w -intstyle ise -ol high -xe c -t 1 top2_map.ncd top2.ncd top2.pcf INFO:Par:338 - Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are not meeting timing but where the designer wants the tools to continue iterating on the design until no further design speed improvements are possible. This can result in very long runtimes since the tools will continue improving the design even if the time specs can not be met. If you are looking for the best possible design speed available from a long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design speed improvements have shrunk to the point that the time specs are not expected to be met. Constraints file: top2.pcf. Loading device for application Rf_Device from file '5vlx50t.nph' in environment C:\Xilinx\10.1\ISE. "top2" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -1 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) Device speed data version: "PRODUCTION 1.62 2008-08-19". Device Utilization Summary: Number of BUFGs 13 out of 32 40% Number of External IOBs 272 out of 480 56% Number of LOCed IOBs 0 out of 272 0% Number of Slice Registers 25344 out of 28800 88% Number used as Flip Flops 25344 Number used as Latches 0 Number used as LatchThrus 0 Number of Slice LUTS 17100 out of 28800 59% Number of Slice LUT-Flip Flop pairs 26135 out of 28800 90% Overall effort level (-ol): High Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 39 secs Finished initial Timing Analysis. REAL time: 40 secs Starting Router Phase 1: 136915 unrouted; REAL time: 43 secs Phase 2: 119040 unrouted; REAL time: 49 secs Phase 3: 34714 unrouted; REAL time: 3 mins 31 secs Phase 4: 34714 unrouted; (526227) REAL time: 3 mins 35 secs Phase 5: 35486 unrouted; (14976) REAL time: 3 mins 46 secs Phase 6: 35455 unrouted; (14419) REAL time: 3 mins 47 secs Phase 7: 1 unrouted; (9222) REAL time: 7 mins 7 secs Total REAL time to Router completion: 7 mins 10 secs Total CPU time to Router completion: 7 mins 8 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clock_BUFGP |BUFGCTRL_X0Y15| No | 6825 | 0.346 | 1.870 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. Timing Score: 9222 WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to ensure the best options are set in the tools for timing closure. Use the Xilinx "SmartXplorer" script to try special combinations of options known to produce very good results. Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ * TS_clock = PERIOD TIMEGRP "clock" 310 MHz | SETUP | -0.422ns| 3.647ns| 69| 9118 HIGH 50% | HOLD | 0.306ns| | 0| 0 ------------------------------------------------------------------------------------------------------ * NET "clock_BUFGP/IBUFG" MAXDELAY = 1.2 ns | MAXDELAY| -0.104ns| 1.304ns| 1| 104 ------------------------------------------------------------------------------------------------------ NET "clock_BUFGP/IBUFG" MAXSKEW = 0.1 ns | NETSKEW | 0.009ns| 0.091ns| 0| 0 ------------------------------------------------------------------------------------------------------ 2 constraints not met. Generating Pad Report. 1 signals are not completely routed. WARNING:Par:100 - Design is not completely routed. Total REAL time to PAR completion: 7 mins 22 secs Total CPU time to PAR completion: 7 mins 20 secs Peak Memory Usage: 770 MB Placer: Placement generated during map. Routing: Completed - errors found. Timing: Completed - 70 errors found. Number of error messages: 0 Number of warning messages: 3 Number of info messages: 2 Writing design to file top2.ncd PAR done!