library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mash_sost is
    Port ( CLK : in std_logic;
           WRITE : out std_logic;
           ADR : out std_logic;
           NACHIND : out std_logic;
           IND : out std_logic;
           STIR : out std_logic;
           KADRPAUSE : out std_logic);
end mash_sost;												  
																					 
architecture Behavioral of mash_sost is

		type state_type is (st_write, st_adr, st_nachind, st_ind, st_stir, st_kadrpause); 
      signal state, next_state : state_type; 

		signal pol_kadr_count : std_logic_vector (14 downto 0) := "000000000000000";

		signal subpole_count : std_logic_vector (3 downto 0) := "0000";


		  
begin

												 
process
																
begin

  IF (CLK'event and CLK = '1') THEN
     if (pol_kadr_count = 20030) then
			pol_kadr_count <= (others => '0');
		  else pol_kadr_count <= pol_kadr_count + 1;
			 if (pol_kadr_count >= 0 and pol_kadr_count < 447 ) then
			     state <= st_write;
			 end if;
				if (subpole_count = 8) then
					subpole_count <= (others => '0');
				else subpole_count <= subpole_count +1;
									  
next_state <= state;
  
  case state is

		 when st_write =>
		      if (pol_kadr_count >= 447 and pol_kadr_count < 2090) or (pol_kadr_count >= 2240 and pol_kadr_count < 3884) or (pol_kadr_count >= 4083 and pol_kadr_count < 5726) 
					or (pol_kadr_count >= 6055 and pol_kadr_count < 7698) or (pol_kadr_count >= 8255 and pol_kadr_count < 9898) or (pol_kadr_count >= 10927 and pol_kadr_count < 12570)
					or (pol_kadr_count >= 14541 and pol_kadr_count < 16184) then next_state <= st_adr;
				end if;
		 
		 when st_adr =>
				if (pol_kadr_count >= 2090 and pol_kadr_count < 2143) or (pol_kadr_count >= 3884 and pol_kadr_count < 3936) or (pol_kadr_count >= 5726 and pol_kadr_count < 5779) 
					or (pol_kadr_count >= 7698 and pol_kadr_count < 7751) or (pol_kadr_count >= 9898 and pol_kadr_count < 9951) or (pol_kadr_count >= 12570 and pol_kadr_count < 12623)
					or (pol_kadr_count >= 16184 and pol_kadr_count < 16237) then next_state <= st_nachind;
		 		end if;
		 
		 when st_nachind =>
				if (pol_kadr_count >= 2143 and pol_kadr_count < 2175) or (pol_kadr_count >= 3936 and pol_kadr_count < 4018 ) or (pol_kadr_count >= 5779 and pol_kadr_count < 5990) 
					or (pol_kadr_count >= 7751 and pol_kadr_count < 8190) or (pol_kadr_count >= 9951 and pol_kadr_count < 10862) or (pol_kadr_count >= 12623 and pol_kadr_count < 14476)
					or (pol_kadr_count >= 16237 and pol_kadr_count < 19960) then next_state <= st_ind;
				end if;
		 
		 when st_ind =>
				if (pol_kadr_count >= 2175 and pol_kadr_count < 2240) or (pol_kadr_count >= 4018 and pol_kadr_count < 4083 ) or (pol_kadr_count >= 5990 and pol_kadr_count < 6055) 
					or (pol_kadr_count >= 8190 and pol_kadr_count < 8255) or (pol_kadr_count >= 10862 and pol_kadr_count < 10927) or (pol_kadr_count >= 14476 and pol_kadr_count <14541 )
					or (pol_kadr_count >= 19960 and pol_kadr_count < 20026) then next_state <= st_stir;
				end if;

		 when st_stir =>
				if (subpole_count <= 7) then  next_state <= st_adr;
				 else next_state <= st_kadrpause;
				end if;
		 when  st_kadrpause =>
				next_state <= st_write;
  end case;


				end if;
     end if;		 	  

END IF;

end process;


process
 
begin
 
	 WRITE <= '0';
	 ADR <= '0';
	 NACHIND <= '0';
	 IND <= '0';
	 STIR <= '0';
	 KADRPAUSE <= '0';

	case state is
		when st_write =>
			WRITE <= '1' ;
		when st_adr =>
			ADR <= '1' ;
		when st_nachind =>
			NACHIND <= '1' ;
		when st_ind =>
			IND <= '1' ;
		when st_stir =>
			STIR <= '1' ;
		when st_kadrpause =>
			KADRPAUSE <= '1' ;
     end case; 
	       
end process;  


end Behavioral;