`timescale 1 ns / 1 ns

module dataEx_tb;

logic WE_MC, OE_MC, CS_MC; 
logic [15:0] adress_MC; 
trireg [15:0] data_MC;
trireg [15:0] data_TDC;
logic WE_TDC, CS_TDC, OE_MC_TDC;
logic [3:0] adress_TDC;

dataEx_v2 dut (
.WE_MC(WE_MC), .OE_MC(OE_MC), .CS_MC(CS_MC), .WE_TDC(WE_TDC), .OE_MC_TDC(OE_MC_TDC), .CS_TDC(CS_TDC),
.data_MC(data_MC), .data_TDC(data_TDC), .adress_MC(adress_MC), .adress_TDC(adress_TDC)
);

initial begin
	OE_MC = 1;
	WE_MC = 1;
	CS_MC = 1;
   data_MC = 16'hz;
	adress_MC = 0;
end

	
initial begin

#200 CS_MC = 0;
	  adress_MC = 16'h5;
#100 WE_MC = 0;
#100 data_MC = 16'hD2334;
#100 WE_MC = 1;
#100 CS_MC = 1;

#200 CS_MC = 0;
	  adress_MC = 16'h18;
#100 WE_MC = 0;
#100 data_MC = 16'h38F57;
#100 WE_MC = 1;
#100 CS_MC = 1;

#200 CS_MC = 0;
	  adress_MC = 16'h3;
#100 WE_MC = 0;
#100 data_MC = 16'h4457;
#100 WE_MC = 1;
#100 CS_MC = 1;

#200 CS_MC = 0;
	  adress_MC = 16'hF;
#100 WE_MC = 0;
#100 data_MC = 16'h9577;
#100 WE_MC = 1;
#100 CS_MC = 1;

#200 CS_MC = 0;
	  adress_MC = 16'h5;
#100 OE_MC = 0;
#100 data_TDC = 16'h7777;
#100 OE_MC = 1;
#100 CS_MC = 1;

#200 CS_MC = 0;
	  adress_MC = 16'h18;
#100 OE_MC = 0;
#100 data_TDC = 16'd38957;
#100 OE_MC = 1;
#100 CS_MC = 1;


end


	
endmodule