# Reading pref.tcl
# //  Questa Sim-64
# //  Version 2021.1 win64 Jan 19 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do {run_behav_compile.tcl}
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap work ./work 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap usim E:/Igor/progect/Pangomicro/Qlibrary/usim 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap adc_e2 E:/Igor/progect/Pangomicro/Qlibrary/adc_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap ddc_e2 E:/Igor/progect/Pangomicro/Qlibrary/ddc_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap dll_e2 E:/Igor/progect/Pangomicro/Qlibrary/dll_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap hsstlp_lane E:/Igor/progect/Pangomicro/Qlibrary/hsstlp_lane 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap hsstlp_pll E:/Igor/progect/Pangomicro/Qlibrary/hsstlp_pll 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap iolhr_dft E:/Igor/progect/Pangomicro/Qlibrary/iolhr_dft 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap ipal_e1 E:/Igor/progect/Pangomicro/Qlibrary/ipal_e1 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap ipal_e2 E:/Igor/progect/Pangomicro/Qlibrary/ipal_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap iserdes_e2 E:/Igor/progect/Pangomicro/Qlibrary/iserdes_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap oserdes_e2 E:/Igor/progect/Pangomicro/Qlibrary/oserdes_e2 
# Modifying modelsim.ini
# QuestaSim-64 vmap 2021.1 Lib Mapping Utility 2021.01 Jan 19 2021
# vmap pciegen2 E:/Igor/progect/Pangomicro/Qlibrary/pciegen2 
# Modifying modelsim.ini
# QuestaSim-64 vlog 2021.1 Compiler 2021.01 Jan 19 2021
# Start time: 15:35:42 on Mar 20,2024
# vlog -reportprogress 300 -work work -source E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/pkg_gen.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/pkg_chk.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/crc32_8bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/crc32_4bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/lfsr.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/rand_gen.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/ips2l_sgmii_dut_top_Ether.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/led/clock_chk.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/reset_and_sync/cross_reset_sync.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_apb_mif_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_clk_gen_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_cmd_parser_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_fifo_top_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_mdio_mif_16bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_uart_ctrl_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_uart_ctrl_top_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_uart_rx_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_uart_top_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/pgr_uart_tx_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/rstn_sync_32bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/fifo/ipm_distributed_fifo_v1_2_pgr_prefetch_fifo.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/fifo/ipm_distributed_sdpram_v1_2_pgr_prefetch_fifo.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/uart_ctrl_32bit/fifo/pgr_prefetch_fifo.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/reg_slave/ipsl_sgmii_reg_slave.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/reg_slave/ips2l_sgmii_sync_chain_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/reg_slave/ips2l_sgmii_sync_spreading_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/debug_core.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_cfg_reg_file_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_data_capture_mem_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_debug_core_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_hub_decode_v1_2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_rd_addr_gen_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_storage_condition_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_trig_unit_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_trigger_condition_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/jtag_hub/jtag_hub.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/jtag_hub/rtl/ips_jtag_hub_v1_2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/ips2l_sgmii_onboard_top.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/synplify/ips2l_sgmii_v1_2_vpAll.vp E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/async_fifo_deep16_width2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/fifo_128depth_16_width.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm_distributed_fifo_ctr_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm_distributed_fifo_v1_2_async_fifo_deep16_width2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm_distributed_sdpram_v1_2_async_fifo_deep16_width2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm2l_fifo_ctrl_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm2l_fifo_v1_2_fifo_128depth_16_width.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ipm2l_sdpram_v1_1_fifo_128depth_16_width.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ips_sgmii_sync_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/common/ips2l_sgmii_apb_union_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/ips_sgmii_ge_pcs_core_v1_11_Ether.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/ips2l_sgmii_core_v1_1_Ether.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/Ether.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/ipm2l_sgmii_hsstlp.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_sgmii_hsstlp_apb_bridge_v1_2.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_sgmii_hsstlp_wrapper_v1_8.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_fifo_clr_v1_3.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_pll_rst_fsm_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_debounce_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_pll_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_rx_v1_6.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_sync_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_tx_v1_6.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_v1_8.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rst_wtchdg_v1_0.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_rxlane_rst_fsm_v1_6.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/rtl/hsstlp/ipm2l_hsstlp/rtl/ipm2l_hsstlp_rst/ipm2l_sgmii_hsstlp_txlane_rst_fsm_v1_6.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/bench/ips2l_sgmii_dut_sim_top.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/bench/ips2l_sgmii_dut_top_tb.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/ips2l_sgmii_dut_top_Ether.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/mdio/mdio.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/mdio/mdio_drv.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/crc32_4bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/crc32_8bit.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/lfsr.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/pkg_chk.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/pkg_gen.v E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/rand_gen.v 
# -- Compiling module pkg_gen
# -- Compiling module pkg_chk
# -- Compiling module crc32_8bit
# -- Compiling module crc32_4bit
# -- Compiling module lfsr
# -- Compiling module rand_gen
# -- Compiling module ips2l_sgmii_dut_top_Ether
# -- Compiling module clock_chk
# -- Compiling module cross_reset_sync
# -- Compiling module pgr_apb_mif_32bit
# -- Compiling module pgr_clk_gen_32bit
# -- Compiling module pgr_cmd_parser_32bit
# -- Compiling module pgr_fifo_top_32bit
# -- Compiling module pgr_mdio_mif_16bit
# -- Compiling module pgr_uart_ctrl_32bit
# -- Compiling module pgr_uart_ctrl_top_32bit
# -- Compiling module pgr_uart_rx_32bit
# -- Compiling module pgr_uart_top_32bit
# -- Compiling module pgr_uart_tx_32bit
# -- Compiling module rstn_sync_32bit
# -- Compiling module ipm_distributed_fifo_v1_2_pgr_prefetch_fifo
# -- Compiling module ipm_distributed_sdpram_v1_2_pgr_prefetch_fifo
# -- Compiling module pgr_prefetch_fifo
# -- Compiling module ipsl_sgmii_reg_slave
# -- Compiling module ips2l_sgmii_sync_chain_v1_0
# -- Compiling module ips2l_sgmii_sync_spreading_v1_0
# -- Compiling module debug_core
# -- Compiling module ips_dbc_cfg_reg_file_v1_0
###### E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_cfg_reg_file_v1_0.v(57):  in protected region.
# ** Error: (vlog-13069) E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_cfg_reg_file_v1_0.v(57): syntax error in protected region.
# 
###### E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_cfg_reg_file_v1_0.v(57):  in protected region.
# ** Error: E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_cfg_reg_file_v1_0.v(57): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?
# -- Compiling module ips_dbc_compare_256b_v1_0
###### E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(50):  in protected region.
# ** Error: (vlog-13069) E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(50): syntax error in protected region.
# 
###### E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(50):  in protected region.
# ** Error: (vlog-13058) E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(50): syntax error in protected region.
# 
###### E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(298): endmodule
# ** Error: E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(298): (vlog-14205) Unexpected end of file encountered in decryption envelope.
# E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/Debug_core/debug_core/rtl/ips_dbc_compare_256b_v1_0.v(298): Verilog Compiler exiting
# End time: 15:35:42 on Mar 20,2024, Elapsed time: 0:00:00
# Errors: 5, Warnings: 0
# ** Error: D:/Win11/Programs/QuestaSim/win64/vlog failed.
# Error in macro ./run_behav_compile.tcl line 98
# D:/Win11/Programs/QuestaSim/win64/vlog failed.
#     while executing
# "vlog -work work -source  \
# "E:/Igor/progect/Pangomicro/Test_0_1/ipcore/Ether/example_design/rtl/pkg_gen/pkg_gen.v" \
# "E:/Igor/progect/Pangomicro/Test_..."
# do {run_behav_simulate.tcl}
# vsim -novopt -L work -L usim -L adc_e2 -L ddc_e2 -L dll_e2 -L hsstlp_lane -L hsstlp_pll -L iolhr_dft -L ipal_e1 -L ipal_e2 -L iserdes_e2 -L oserdes_e2 -L pciegen2 ips2l_sgmii_dut_top_tb usim.GTP_GRS 
# Start time: 15:35:42 on Mar 20,2024
# ** Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./run_behav_simulate.tcl PAUSED at line 6