start_gui open_project D:/Projects_Vivado/test_v_tpg/test_v_tpg.xpr open_project D:/Projects_Vivado/test_v_tpg/test_v_tpg.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2017.1/data/ip'. WARNING: [IP_Flow 19-3664] IP 'design_1_v_tpg_0_1' generated file not found 'd:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_1_v_tpg_0_1' generated file not found 'd:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_1_v_tpg_0_1' generated file not found 'd:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_1_v_tpg_0_1' generated file not found 'd:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1_sim_netlist.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'design_1_v_tpg_0_1' generated file not found 'd:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1_sim_netlist.vhdl'. Please regenerate to continue. open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 864.645 ; gain = 70.680 update_compile_order -fileset sources_1 open_bd_design {D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd} Adding cell -- xilinx.com:ip:v_tpg:7.0 - v_tpg_0 Successfully read diagram from BD file open_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 936.418 ; gain = 22.582 reset_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -sync -no_script -force -quiet delete_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] generate_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.v Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block v_tpg_0 . Exporting to file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Block Design Tcl file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl Generated Hardware Definition File D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.hwdef generate_target: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1038.891 ; gain = 60.516 catch { config_ip_cache -export [get_ips -all design_1_v_tpg_0_1] } export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] launch_runs -jobs 4 design_1_v_tpg_0_1_synth_1 [Wed Feb 9 10:14:33 2022] Launched design_1_v_tpg_0_1_synth_1... Run output will be captured here: D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1/runme.log export_simulation -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/sim_scripts -ip_user_files_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files -ipstatic_source_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/modelsim} {questa=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/questa} {riviera=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/riviera} {activehdl=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet reset_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -sync -no_script -force -quiet delete_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] WARNING: [Vivado 12-1017] Problems encountered: 1. Failed to delete one or more files in run directory D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1 generate_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.v Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block v_tpg_0 . Exporting to file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Block Design Tcl file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl Generated Hardware Definition File D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.hwdef catch { config_ip_cache -export [get_ips -all design_1_v_tpg_0_1] } export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] launch_runs -jobs 4 design_1_v_tpg_0_1_synth_1 [Wed Feb 9 10:36:11 2022] Launched design_1_v_tpg_0_1_synth_1... Run output will be captured here: D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1/runme.log export_simulation -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/sim_scripts -ip_user_files_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files -ipstatic_source_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/modelsim} {questa=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/questa} {riviera=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/riviera} {activehdl=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet report_ip_status -name ip_status report_ip_status: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1075.125 ; gain = 0.000 reset_run synth_1 launch_runs synth_1 -jobs 4 [Wed Feb 9 10:37:11 2022] Launched design_1_v_tpg_0_1_synth_1... Run output will be captured here: D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1/runme.log [Wed Feb 9 10:37:11 2022] Launched synth_1... Run output will be captured here: D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/synth_1/runme.log config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo config_ip_cache -clear_output_repo reset_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -sync -no_script -force -quiet delete_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] WARNING: [Vivado 12-1017] Problems encountered: 1. Failed to delete one or more files in run directory D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1 generate_target all [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] INFO: [BD 41-1662] The design 'design_1.bd' is already validated. Therefore parameter propagation will not be re-run. Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.v Verilog Output written to : D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v INFO: [BD 41-1029] Generation completed for the IP Integrator block v_tpg_0 . Exporting to file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh Generated Block Design Tcl file D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl Generated Hardware Definition File D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/hdl/design_1.hwdef catch { config_ip_cache -export [get_ips -all design_1_v_tpg_0_1] } export_ip_user_files -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -no_script -sync -force -quiet create_ip_run [get_files -of_objects [get_fileset sources_1] D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] launch_runs -jobs 4 design_1_v_tpg_0_1_synth_1 [Wed Feb 9 10:50:29 2022] Launched design_1_v_tpg_0_1_synth_1... Run output will be captured here: D:/Projects_Vivado/test_v_tpg/test_v_tpg.runs/design_1_v_tpg_0_1_synth_1/runme.log export_simulation -of_objects [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/design_1.bd] -directory D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/sim_scripts -ip_user_files_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files -ipstatic_source_dir D:/Projects_Vivado/test_v_tpg/test_v_tpg.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/modelsim} {questa=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/questa} {riviera=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/riviera} {activehdl=D:/Projects_Vivado/test_v_tpg/test_v_tpg.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet set_property location {-78 -258} [get_bd_intf_ports s_axi_CTRL] set_property location {-83 -255} [get_bd_intf_ports s_axi_CTRL] set_property location {-83 -236} [get_bd_ports ap_clk] set_property location {-85 -228} [get_bd_ports ap_clk] set_property location {-81 -254} [get_bd_intf_ports s_axi_CTRL] set_property location {-81 -215} [get_bd_ports ap_rst_n] save_bd_design Wrote : regenerate_bd_layout save_bd_design Wrote : file mkdir ./tmp_dir file copy D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1.xci ./tmp_dir create_project -in_memory -part xc7z020clg484-1 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2017.1/data/ip'. Project read_ip ./tmp_dir/design_1_v_tpg_0_1.xci d:/Projects_Vivado/test_v_tpg/tmp_dir/design_1_v_tpg_0_1.xci generate_target all [get_files design_1_v_tpg_0_1.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'design_1_v_tpg_0_1'... INFO: [IP_Flow 19-1686] Generating 'High-Level Synthesis C source' target for IP 'design_1_v_tpg_0_1'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'design_1_v_tpg_0_1'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'design_1_v_tpg_0_1'... INFO: [IP_Flow 19-1686] Generating 'Miscellaneous' target for IP 'design_1_v_tpg_0_1'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'design_1_v_tpg_0_1'... compile_c [get_files design_1_v_tpg_0_1.xci] ================================================================ Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC Version 2017.1 Build 1846317 on Fri Apr 14 19:19:38 MDT 2017 Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. ================================================================ INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado_HLS/2017.1/bin/unwrapped/win64.o/vivado_hls.exe' INFO: [HLS 200-10] For user 'yvklesova' on host 'ws219' (Windows NT_amd64 version 6.1) on Wed Feb 09 13:11:16 +0300 2022 INFO: [HLS 200-10] In directory 'D:/Projects_Vivado/test_v_tpg' INFO: [HLS 200-10] Creating and opening project 'D:/Projects_Vivado/test_v_tpg/design_1_v_tpg_0_1'. INFO: [HLS 200-10] Adding design file 'd:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg_config.h' to the project INFO: [HLS 200-10] Adding design file 'd:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp' to the project INFO: [HLS 200-10] Adding design file 'd:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.h' to the project INFO: [HLS 200-10] Adding design file 'd:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg_zoneplate.h' to the project INFO: [HLS 200-10] Creating and opening solution 'D:/Projects_Vivado/test_v_tpg/design_1_v_tpg_0_1/prj'. INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-1' INFO: [SYN 201-201] Setting up clock 'ap_clk' with a period of 6.667ns. INFO: [HLS 200-10] Analyzing design file 'd:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp' ... INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:02 ; elapsed = 00:01:10 . Memory (MB): peak = 163.953 ; gain = 111.840 INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:02 ; elapsed = 00:01:45 . Memory (MB): peak = 164.156 ; gain = 112.043 INFO: [HLS 200-10] Starting code transformations ... INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:17 ; elapsed = 00:02:35 . Memory (MB): peak = 567.090 ; gain = 514.977 INFO: [HLS 200-10] Checking synthesizability ... WARNING: [SYNCHK 200-23] d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:901: variable-indexed range selection may cause suboptimal QoR. INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s). INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:25 ; elapsed = 00:02:55 . Memory (MB): peak = 634.551 ; gain = 582.438 INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternZonePlate'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternVerticalRamp'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternVerticalHorizontalRamp'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternTemporalRamp'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternTartanColorBars'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternSolidWhite'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternSolidRed'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternSolidGreen'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternSolidBlue'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternSolidBlack'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternRainbow'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternMask'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternHorizontalRamp'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternDPColorSquare'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternDPColorRamp'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternDPBlackWhiteVerticalLine'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternCrossHatch'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternCrossHair'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternColorBars'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternCheckerBoard'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPatternBox'. INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'tpgPRBS'. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1.1' in function 'tpgForeground' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1.1' in function 'tpgBackground' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1.1' (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:865) in function 'MultiPixStream2AXIvideo' for pipelining. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternZonePlate' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternVerticalRamp' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternVerticalHorizontalRamp' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternTemporalRamp' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternTartanColorBars' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternSolidWhite' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternSolidRed' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternSolidGreen' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternSolidBlue' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternSolidBlack' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternRainbow' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternMask' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-2' in function 'tpgPatternMask' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternHorizontalRamp' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternDPColorSquare' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternDPColorRamp' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternDPBlackWhiteVerticalLine' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternCrossHatch' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternCrossHair' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternColorBars' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternCheckerBoard' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPatternBox' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1' in function 'tpgPRBS' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.2' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.3' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.4' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.5' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.6' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.7' in function 'tpgForeground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.2' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.3' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.4' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.5' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.6' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.7' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.8' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.9' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.10' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.11' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.12' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.13' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.14' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.15' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.16' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.17' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.18' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.19' in function 'tpgBackground' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.1' (D:/Xilinx/Vivado_HLS/2017.1/common/technology/autopilot/hls/hls_video_core.h:171) in function 'MultiPixStream2AXIvideo' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.2' (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:889) in function 'MultiPixStream2AXIvideo' completely. INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1.2.1' (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:891) in function 'MultiPixStream2AXIvideo' completely. INFO: [XFORM 203-102] Partitioning array 'xCount.V.3' automatically. INFO: [XFORM 203-102] Partitioning array 'xCount.V.2' automatically. INFO: [XFORM 203-102] Partitioning array 'xCount.V.1' automatically. INFO: [XFORM 203-102] Partitioning array 'xCount.V' automatically. INFO: [XFORM 203-102] Partitioning array 'xBar.V' automatically. INFO: [XFORM 203-102] Partitioning array 'hBarSel.5' automatically. INFO: [XFORM 203-102] Partitioning array 'hBarSel.4' automatically. INFO: [XFORM 203-102] Partitioning array 'hBarSel.3' automatically. INFO: [XFORM 203-102] Partitioning array 'hBarSel' automatically. INFO: [XFORM 203-102] Automatically partitioning streamed array 'ovrlayYUV.V.val.V' . INFO: [XFORM 203-102] Automatically partitioning streamed array 'bckgndYUV.V.val.V' . INFO: [XFORM 203-101] Partitioning array 'pix.val.V' (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:820) in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'tmp.val.V' in dimension 1 completely. INFO: [XFORM 203-712] Applying dataflow to function 'v_tpg', detected/extracted 3 process function(s): 'tpgBackground' 'tpgForeground' 'MultiPixStream2AXIvideo'. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternVerticalHorizontalRamp'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternTartanColorBars'... converting 13 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternSolidWhite'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternSolidRed'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternSolidGreen'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternSolidBlue'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternSolidBlack'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternRainbow'... converting 10 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternDPColorSquare'... converting 14 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternDPColorRamp'... converting 11 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternCrossHatch'... converting 12 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternCrossHair'... converting 7 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternColorBars'... converting 13 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternCheckerBoard'... converting 13 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPatternBox'... converting 5 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'tpgPRBS'... converting 6 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:866:10) to (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:865:53) in function 'MultiPixStream2AXIvideo'... converting 13 basic blocks. INFO: [XFORM 203-11] Balancing expressions in function 'tpgPatternRainbow'...3 expression(s) balanced. INFO: [XFORM 203-11] Balancing expressions in function 'tpgPatternBox'...3 expression(s) balanced. INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:36 ; elapsed = 00:03:19 . Memory (MB): peak = 837.484 ; gain = 785.371 WARNING: [XFORM 203-631] Renaming function 'tpgPatternVerticalRamp' into tpgPatternVerticalRa. WARNING: [XFORM 203-631] Renaming function 'tpgPatternVerticalHorizontalRamp' into tpgPatternVerticalHo. WARNING: [XFORM 203-631] Renaming function 'tpgPatternTemporalRamp' into tpgPatternTemporalRa. WARNING: [XFORM 203-631] Renaming function 'tpgPatternTartanColorBars' into tpgPatternTartanColo. WARNING: [XFORM 203-631] Renaming function 'tpgPatternHorizontalRamp' into tpgPatternHorizontal. WARNING: [XFORM 203-631] Renaming function 'tpgPatternDPColorSquare' into tpgPatternDPColorSqu. WARNING: [XFORM 203-631] Renaming function 'tpgPatternDPColorRamp' into tpgPatternDPColorRam. WARNING: [XFORM 203-631] Renaming function 'tpgPatternDPBlackWhiteVerticalLine' into tpgPatternDPBlackWhi. WARNING: [XFORM 203-631] Renaming function 'tpgPatternCheckerBoard' into tpgPatternCheckerBoa. WARNING: [XFORM 203-631] Renaming function 'MultiPixStream2AXIvideo' (d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:171:53) into MultiPixStream2AXIvi. WARNING: [SYN 201-506] Unknown intrinsic op [_ssdm_op_SpecLicense] WARNING: [SYN 201-506] Unknown intrinsic op [_ssdm_op_SpecLicense] WARNING: [SYN 201-506] Unknown intrinsic op [_ssdm_op_SpecLicense] INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:42 ; elapsed = 00:03:31 . Memory (MB): peak = 1239.090 ; gain = 1186.977 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'v_tpg' ... WARNING: [SYN 201-103] Legalizing function name 'reg >' to 'reg_ap_uint_10_s'. WARNING: [SYN 201-103] Legalizing function name 'reg' to 'reg_int_s'. WARNING: [SYN 201-103] Legalizing function name 'reg' to 'reg_unsigned_short_s'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternDPColorSqu' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 7 0 11 100 22 2 3 1.9 2 14 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternDPColorSqu'. WARNING: [SCHED 204-70] Unable to enforce a clock period constraint between 'icmp' operation ('tmp_55', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1531) and 'and' operation ('or_cond_26', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1531). WARNING: [SCHED 204-70] In llvm assembly, the node are: . INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 6. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... WARNING: [SCHED 204-21] Estimated clock period (5.95ns) exceeds the target (target clock period: 6.67ns, clock uncertainty: 0.833ns, effective delay budget: 5.83ns). WARNING: [SCHED 204-21] The critical path consists of the following: 'load' operation ('yCount_V_load') on static variable 'yCount_V' (0 ns) 'icmp' operation ('tmp_55', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1531) (3.88 ns) 'and' operation ('or_cond_26', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1531) (2.07 ns) INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 211.138 seconds; current allocated memory: 1.103 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 4.044 seconds; current allocated memory: 1.103 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternDPBlackWhi' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 0 6 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternDPBlackWhi'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 1. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.986 seconds; current allocated memory: 1.103 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.409 seconds; current allocated memory: 1.103 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternDPColorRam' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 6 0 4 28 10 2.5 3 2.5 3 6 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternDPColorRam'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.393 seconds; current allocated memory: 1.103 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 1.278 seconds; current allocated memory: 1.103 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPRBS' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 6 0 1 21 4 4 4 4 4 1 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPRBS'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 1. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 1.189 seconds; current allocated memory: 1.103 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 1.536 seconds; current allocated memory: 1.103 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternCheckerBoa' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 9 0 5 80 12 2.4 3 2.4 3 7 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternCheckerBoa'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 6. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 1.453 seconds; current allocated memory: 1.104 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.353 seconds; current allocated memory: 1.104 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternVerticalHo' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 0 16 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternVerticalHo'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 2. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.722 seconds; current allocated memory: 1.104 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.759 seconds; current allocated memory: 1.104 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternRainbow' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('b', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1099) b constant -21 c 'mul' operation ('tmp_164_cast', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) INFO: [SYN 201-351] DSP48 Expression: tmp4 = tmp_164_cast + tmp_152_cast_cast_ca * -21 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('p_tmp_s', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1097) b constant -43 c 'add' operation ('tmp2', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1112) INFO: [SYN 201-351] DSP48 Expression: tmp_56 = tmp2 + tmp_148_cast5_cast1 * -43 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('g', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1098) b constant -85 c constant -32640 INFO: [SYN 201-351] DSP48 Expression: tmp2 = tmp_150_cast * -85 + -32640 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('b', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1099) b constant 29 c 'add' operation ('tmp_52', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1111) INFO: [SYN 201-351] DSP48 Expression: tmp_53 = tmp_152_cast_cast_ca * 29 + tmp_155_cast INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('g', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1098) b constant 150 c 'add' operation ('tmp_51', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1111) INFO: [SYN 201-351] DSP48 Expression: tmp_52 = tmp_150_cast * 150 + tmp_154_cast INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'select' operation ('p_tmp_s', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1097) b constant 77 c constant 4224 INFO: [SYN 201-351] DSP48 Expression: tmp_51 = tmp_148_cast5_cast1 * 77 + 4224 INFO: [SYN 201-351] The following objects are mapped to a ternary adder tree. INFO: [SYN 201-351] a 'add' operation ('tmp4', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) b constant 32896 c 'bitconcatenate' operation ('tmp_58', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 14 0 10 61 22 2.2 3 2.1 3 16 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternRainbow'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 10. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... WARNING: [SCHED 204-21] Estimated clock period (8.35ns) exceeds the target (target clock period: 6.67ns, clock uncertainty: 0.833ns, effective delay budget: 5.83ns). WARNING: [SCHED 204-21] The critical path consists of the following: 'mul' operation ('tmp_165_cast', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) (3.36 ns) 'add' operation ('tmp4', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) (3.02 ns) 'add' operation ('tmp_59', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1113) (1.97 ns) INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.768 seconds; current allocated memory: 1.105 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.53 seconds; current allocated memory: 1.105 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'reg_ap_uint_10_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 2 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'reg >'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 2. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.476 seconds; current allocated memory: 1.105 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.509 seconds; current allocated memory: 1.105 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternCrossHatch' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 10 0 4 79 11 2.8 3 2 2 8 1 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternCrossHatch'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 4. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.448 seconds; current allocated memory: 1.105 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.505 seconds; current allocated memory: 1.106 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternTartanColo' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 9 0 5 78 12 2.4 3 2.4 3 7 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternTartanColo'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 6. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.5 seconds; current allocated memory: 1.106 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.473 seconds; current allocated memory: 1.106 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'reg_int_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 2 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'reg'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 2. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.416 seconds; current allocated memory: 1.106 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.648 seconds; current allocated memory: 1.106 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternZonePlate' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a 'load' operation ('tpgSinTableArray_loa', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1173) on array 'tpgSinTableArray' b constant 221 INFO: [SYN 201-351] DSP48 Expression: tmp_31_tr = 221 * tmp_16 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a wire read on port 'Zplate_Hor_Control_D' b 'call' operation ('tmp_11', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1167) to 'reg' c 'add' operation ('tmp1', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1171) INFO: [SYN 201-351] DSP48 Expression: tmp_14 = tmp1 + Zplate_Hor_Control_D_1 * tmp_21 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a wire read on port 'Zplate_Hor_Control_S' b wire read on port 'x' c 'phi' operation ('zonePlateVAddr_loc_1', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1153) with incoming values : ('zonePlateVAddr_load', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1162) ('tmp_5', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1162) ('tmp_2', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1153) INFO: [SYN 201-351] DSP48 Expression: tmp1 = Zplate_Hor_Control_S_1 * x_read + zonePlateVAddr_loc_1 INFO: [SYN 201-351] The following objects are mapped to a DSP48. INFO: [SYN 201-351] a constant -1 b wire read on port 'x' d wire read on port 'x' INFO: [SYN 201-351] DSP48 Expression: tmp_8 = (-1 + tmp_7_cast) * tmp_7 ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 4 0 2 46 4 2 2 2 2 1 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternZonePlate'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 9. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... WARNING: [SCHED 204-21] Estimated clock period (6.38ns) exceeds the target (target clock period: 6.67ns, clock uncertainty: 0.833ns, effective delay budget: 5.83ns). WARNING: [SCHED 204-21] The critical path consists of the following: wire read on port 'x' (0 ns) 'mul' operation ('tmp_8', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1167) (6.38 ns) INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.442 seconds; current allocated memory: 1.107 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 2.223 seconds; current allocated memory: 1.107 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternColorBars' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SYN 201-351] The following objects are mapped to a ternary adder tree. INFO: [SYN 201-351] a 'load' operation ('xBar_V_0_load', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1072) on static variable 'xBar_V_0' b constant 1 c 'partselect' operation ('barWidth.V', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1063) ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 5 0 4 52 10 2.5 3 2.5 3 7 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternColorBars'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 4. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 2.201 seconds; current allocated memory: 1.107 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 2.394 seconds; current allocated memory: 1.107 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternSolidWhite' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 2 0 1 14 3 3 3 2 2 2 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternSolidWhite'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 2.236 seconds; current allocated memory: 1.107 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.774 seconds; current allocated memory: 1.107 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternSolidBlack' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 1 14 3 3 3 2 2 2 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternSolidBlack'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.837 seconds; current allocated memory: 1.107 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.8 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternSolidBlue' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 1 16 3 3 3 2 2 2 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternSolidBlue'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.721 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.798 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternSolidGreen' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 1 16 3 3 3 2 2 2 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternSolidGreen'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.773 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.884 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternSolidRed' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 2 0 2 17 5 2.5 3 2 2 3 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternSolidRed'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.776 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.943 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternTemporalRa' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 8 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternTemporalRa'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 1. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.917 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.479 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternVerticalRa' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 1 0 1 22 2 2 2 2 2 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternVerticalRa'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 2. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.438 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.986 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternHorizontal' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 14 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternHorizontal'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 2. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.943 seconds; current allocated memory: 1.108 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.69 seconds; current allocated memory: 1.108 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgBackground' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 182 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining loop 'Loop 1.1'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 13. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.669 seconds; current allocated memory: 1.109 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 8.52 seconds; current allocated memory: 1.111 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternBox' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 8 0 5 74 12 2.4 5 2 3 4 1 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternBox'. WARNING: [SCHED 204-70] Unable to enforce a clock period constraint between 'icmp' operation ('tmp_113', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1655) and 'select' operation ('storemerge', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1674). WARNING: [SCHED 204-70] In llvm assembly, the node are: . INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 5. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... WARNING: [SCHED 204-21] Estimated clock period (6.87ns) exceeds the target (target clock period: 6.67ns, clock uncertainty: 0.833ns, effective delay budget: 5.83ns). WARNING: [SCHED 204-21] The critical path consists of the following: 'load' operation ('boxHCoord_load', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1659) on static variable 'boxHCoord' (0 ns) 'icmp' operation ('tmp_113', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1655) (3.03 ns) multiplexor before 'phi' operation ('tmp_114') (1.77 ns) 'phi' operation ('tmp_114') (0 ns) 'select' operation ('storemerge', d:/Projects_Vivado/test_v_tpg/tmp_dir/src/v_tpg.cpp:1674) (2.07 ns) INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 7.907 seconds; current allocated memory: 1.111 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.167 seconds; current allocated memory: 1.112 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternCrossHair' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 3 0 3 27 7 2.3 3 2 2 6 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternCrossHair'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.241 seconds; current allocated memory: 1.112 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 1.169 seconds; current allocated memory: 1.112 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgPatternMask' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 3 0 3 16 6 2 2 2 2 3 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining function 'tpgPatternMask'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 1. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 1.074 seconds; current allocated memory: 1.112 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.796 seconds; current allocated memory: 1.112 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'tpgForeground' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 54 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining loop 'Loop 1.1'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 9. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.785 seconds; current allocated memory: 1.112 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 2.432 seconds; current allocated memory: 1.113 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'reg_unsigned_short_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 2 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 2.312 seconds; current allocated memory: 1.113 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.479 seconds; current allocated memory: 1.113 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'MultiPixStream2AXIvi' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 3 0 0 32 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-61] Pipelining loop 'Loop 1.1'. INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 1, Depth: 3. INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.429 seconds; current allocated memory: 1.113 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 3.651 seconds; current allocated memory: 1.113 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Implementing module 'v_tpg' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... ### Num NTree NLUT EssAll EssLUT Size MSize Lev MLev Sel Phy #### 0 0 0 23 0 -nan(ind) 0 -nan(ind) 0 0 0 INFO: [SCHED 204-11] Generating True dependence constraints ... INFO: [SCHED 204-11] Generating Auxiliary dependence constraints ... INFO: [SCHED 204-11] Generating Ternary mapping constraints ... INFO: [SCHED 204-11] Generating Lut Grouping constraints ... INFO: [SCHED 204-11] Generating Node latency constraints ... INFO: [SCHED 204-11] Generating Relative time constraints ... INFO: [SCHED 204-11] Generating Protocol constraints ... INFO: [SCHED 204-11] Generating Precedence constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Pipeline constraints ... INFO: [SCHED 204-11] Generating DSP mapping constraints ... INFO: [SCHED 204-11] Generating Supporting dependence constraints ... INFO: [SCHED 204-11] Generating Resource constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Latency constraints ... INFO: [SCHED 204-11] Generating Cycle time constraints ... INFO: [SCHED 204-11] Generating Blocking node constraints ... INFO: [SCHED 204-11] Generating Chaining constraints ... INFO: [SCHED 204-11] Generating Operation gating constraints ... INFO: [SCHED 204-11] Generating Variable bound constraints ... INFO: [SCHED 204-11] Generating PHI node constraints ... INFO: [SCHED 204-11] Start checking consistency (resolving sdc graph) ... INFO: [SCHED 204-11] Finished checking consistency. INFO: [SCHED 204-11] Start scheduling optimization (solving LP) ... INFO: [SCHED 204-11] Finished scheduling optimization. INFO: [SCHED 204-11] Start constructing STG ... INFO: [SCHED 204-11] Finished constructing STG. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 3.583 seconds; current allocated memory: 1.113 GB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 4.543 seconds; current allocated memory: 1.114 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternDPColorSqu' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'vBarSel_2' is power-on initialization. WARNING: [RTGEN 206-101] Register 'yCount_V' is power-on initialization. WARNING: [RTGEN 206-101] Register 'hBarSel_3_0' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarArray' to 'tpgPatternDPColorbkb' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_VESA_5' to 'tpgPatternDPColorcud' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_VESA_4' to 'tpgPatternDPColordEe' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_VESA_1' to 'tpgPatternDPColoreOg' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_CEA_r' to 'tpgPatternDPColorfYi' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_CEA_g' to 'tpgPatternDPColorg8j' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelRgb_CEA_b' to 'tpgPatternDPColorhbi' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_601_y' to 'tpgPatternDPColoribs' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_709_y' to 'tpgPatternDPColorjbC' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_601_u' to 'tpgPatternDPColorkbM' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_601_v' to 'tpgPatternDPColorlbW' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_709_u' to 'tpgPatternDPColormb6' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternDPColorSqu_DPtpgBarSelYuv_709_v' to 'tpgPatternDPColorncg' due to the length limit 20 WARNING: [RTGEN 206-101] Register 'xCount_V_0' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternDPColorSqu'. INFO: [HLS 200-111] Elapsed time: 4.272 seconds; current allocated memory: 1.115 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternDPBlackWhi' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternDPBlackWhi'. INFO: [HLS 200-111] Elapsed time: 4.157 seconds; current allocated memory: 1.116 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternDPColorRam' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'rampVal_1' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternDPColorRam'. INFO: [HLS 200-111] Elapsed time: 0.477 seconds; current allocated memory: 1.116 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPRBS' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'rSerie_V' is power-on initialization. WARNING: [RTGEN 206-101] Register 'gSerie_V' is power-on initialization. WARNING: [RTGEN 206-101] Register 'bSerie_V' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPRBS'. INFO: [HLS 200-111] Elapsed time: 1.268 seconds; current allocated memory: 1.116 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternCheckerBoa' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'vBarSel_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'yCount_V_5' is power-on initialization. WARNING: [RTGEN 206-101] Register 'hBarSel_4_0' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgCheckerBoardArray' to 'tpgPatternCheckerocq' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelRgb_r265' to 'tpgPatternCheckerpcA' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelYuv_y262' to 'tpgPatternCheckerqcK' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelRgb_g268' to 'tpgPatternCheckerrcU' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelYuv_v256' to 'tpgPatternCheckersc4' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelYuv_u259' to 'tpgPatternCheckertde' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCheckerBoa_tpgBarSelRgb_b271' to 'tpgPatternCheckerudo' due to the length limit 20 WARNING: [RTGEN 206-101] Register 'xCount_V_1_0' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternCheckerBoa'. INFO: [HLS 200-111] Elapsed time: 1.613 seconds; current allocated memory: 1.117 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternVerticalHo' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'hdata' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternVerticalHo'. INFO: [HLS 200-111] Elapsed time: 3.409 seconds; current allocated memory: 1.117 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternRainbow' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternRainbow_tpgSinTableArray_9bi_1' to 'tpgPatternRainbowvdy' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mul_8ns_8s_16_3' to 'v_tpg_mul_8ns_8s_wdI' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_8s_16s_16_1' to 'v_tpg_mac_muladd_xdS' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_8ns_14ns_15_1' to 'v_tpg_mac_muladd_yd2' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_7s_16s_16_1' to 'v_tpg_mac_muladd_zec' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_9ns_15ns_16_1' to 'v_tpg_mac_muladd_Aem' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_6ns_16ns_17_1' to 'v_tpg_mac_muladd_Bew' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_8ns_6s_16ns_16_1' to 'v_tpg_mac_muladd_CeG' due to the length limit 20 INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_Aem': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_Bew': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_CeG': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_xdS': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_yd2': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_zec': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mul_8ns_8s_wdI': 1 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternRainbow'. INFO: [HLS 200-111] Elapsed time: 0.824 seconds; current allocated memory: 1.118 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'reg_ap_uint_10_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_ap_uint_10_s'. INFO: [HLS 200-111] Elapsed time: 3.341 seconds; current allocated memory: 1.118 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternCrossHatch' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'yCount_V_4' is power-on initialization. WARNING: [RTGEN 206-101] Register 'vHatch' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternCrossHatch_whiYuv_1' to 'tpgPatternCrossHaDeQ' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternCrossHatch_blkYuv_1' to 'tpgPatternCrossHaEe0' due to the length limit 20 WARNING: [RTGEN 206-101] Register 'xCount_V_2_0' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternCrossHatch'. INFO: [HLS 200-111] Elapsed time: 0.513 seconds; current allocated memory: 1.119 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternTartanColo' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'vBarSel' is power-on initialization. WARNING: [RTGEN 206-101] Register 'yCount_V_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'hBarSel_5_0' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgTartanBarArray' to 'tpgPatternTartanCFfa' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelRgb_r264' to 'tpgPatternTartanCGfk' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelYuv_y261' to 'tpgPatternTartanCHfu' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelRgb_g267' to 'tpgPatternTartanCIfE' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelYuv_v255' to 'tpgPatternTartanCJfO' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelYuv_u258' to 'tpgPatternTartanCKfY' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternTartanColo_tpgBarSelRgb_b270' to 'tpgPatternTartanCLf8' due to the length limit 20 WARNING: [RTGEN 206-101] Register 'xCount_V_3_0' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternTartanColo'. INFO: [HLS 200-111] Elapsed time: 3.469 seconds; current allocated memory: 1.120 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'reg_int_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_int_s'. INFO: [HLS 200-111] Elapsed time: 3.388 seconds; current allocated memory: 1.120 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternZonePlate' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'zonePlateVAddr' is power-on initialization. WARNING: [RTGEN 206-101] Register 'zonePlateVDelta' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternZonePlate_tpgSinTableArray' to 'tpgPatternZonePlaMgi' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_am_addmul_1s_16ns_16ns_32_1' to 'v_tpg_am_addmul_1Ngs' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_16s_16s_16ns_16_1' to 'v_tpg_mac_muladd_OgC' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mac_muladd_16s_16s_16s_16_1' to 'v_tpg_mac_muladd_PgM' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'v_tpg_mul_mul_9ns_20s_28_1' to 'v_tpg_mul_mul_9nsQgW' due to the length limit 20 INFO: [RTGEN 206-100] Generating core module 'v_tpg_am_addmul_1Ngs': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_OgC': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mac_muladd_PgM': 1 instance(s). INFO: [RTGEN 206-100] Generating core module 'v_tpg_mul_mul_9nsQgW': 1 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternZonePlate'. INFO: [HLS 200-111] Elapsed time: 0.499 seconds; current allocated memory: 1.120 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternColorBars' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'hBarSel_0' is power-on initialization. INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelRgb_r263' to 'tpgPatternColorBaRg6' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelYuv_y260' to 'tpgPatternColorBaShg' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelRgb_g266' to 'tpgPatternColorBaThq' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelYuv_v254' to 'tpgPatternColorBaUhA' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelYuv_u257' to 'tpgPatternColorBaVhK' due to the length limit 20 INFO: [SYN 201-210] Renamed object name 'tpgPatternColorBars_tpgBarSelRgb_b269' to 'tpgPatternColorBaWhU' due to the length limit 20 WARNING: [RTGEN 206-101] Register 'xBar_V_0' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternColorBars'. INFO: [HLS 200-111] Elapsed time: 2.175 seconds; current allocated memory: 1.121 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternSolidWhite' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternSolidWhite_whiYuv' to 'tpgPatternSolidWhXh4' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternSolidWhite'. INFO: [HLS 200-111] Elapsed time: 2.291 seconds; current allocated memory: 1.121 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternSolidBlack' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternSolidBlack_blkYuv' to 'tpgPatternSolidBlYie' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternSolidBlack'. INFO: [HLS 200-111] Elapsed time: 0.789 seconds; current allocated memory: 1.122 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternSolidBlue' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternSolidBlue_bluYuv' to 'tpgPatternSolidBlZio' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternSolidBlue'. INFO: [HLS 200-111] Elapsed time: 0.833 seconds; current allocated memory: 1.122 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternSolidGreen' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternSolidGreen_grnYuv' to 'tpgPatternSolidGr0iy' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternSolidGreen'. INFO: [HLS 200-111] Elapsed time: 0.826 seconds; current allocated memory: 1.122 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternSolidRed' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternSolidRed_redYuv' to 'tpgPatternSolidRe1iI' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternSolidRed'. INFO: [HLS 200-111] Elapsed time: 0.823 seconds; current allocated memory: 1.123 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternTemporalRa' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternTemporalRa'. INFO: [HLS 200-111] Elapsed time: 0.873 seconds; current allocated memory: 1.123 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternVerticalRa' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'rampVal_2' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternVerticalRa'. INFO: [HLS 200-111] Elapsed time: 0.528 seconds; current allocated memory: 1.123 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternHorizontal' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'rampVal' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternHorizontal'. INFO: [HLS 200-111] Elapsed time: 0.984 seconds; current allocated memory: 1.123 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgBackground' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'rampStart' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgBackground'. INFO: [HLS 200-111] Elapsed time: 0.84 seconds; current allocated memory: 1.125 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternBox' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Register 'boxHCoord' is power-on initialization. WARNING: [RTGEN 206-101] Register 'boxVCoord' is power-on initialization. WARNING: [RTGEN 206-101] Register 'hDir' is power-on initialization. WARNING: [RTGEN 206-101] Register 'vDir' is power-on initialization. INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternBox'. INFO: [HLS 200-111] Elapsed time: 7.787 seconds; current allocated memory: 1.126 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternCrossHair' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SYN 201-210] Renamed object name 'tpgPatternCrossHair_whiYuv_2' to 'tpgPatternCrossHa2iS' due to the length limit 20 INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternCrossHair'. INFO: [HLS 200-111] Elapsed time: 3.072 seconds; current allocated memory: 1.126 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgPatternMask' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgPatternMask'. INFO: [HLS 200-111] Elapsed time: 1.143 seconds; current allocated memory: 1.127 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'tpgForeground' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'tpgForeground'. INFO: [HLS 200-111] Elapsed time: 0.862 seconds; current allocated memory: 1.128 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'reg_unsigned_short_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'reg_unsigned_short_s'. INFO: [HLS 200-111] Elapsed time: 2.426 seconds; current allocated memory: 1.128 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'MultiPixStream2AXIvi' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'MultiPixStream2AXIvi'. INFO: [HLS 200-111] Elapsed time: 0.506 seconds; current allocated memory: 1.129 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'v_tpg' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/height' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/width' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/bckgndId' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/ovrlayId' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/maskId' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/motionSpeed' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/colorFormat' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/crossHairX' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/crossHairY' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/ZplateHorContStart' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/ZplateHorContDelta' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/ZplateVerContStart' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/ZplateVerContDelta' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/boxSize' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/boxColorR' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/boxColorG' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/boxColorB' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/dpDynamicRange' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/dpYUVCoef' to 's_axilite & ap_stable'. INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_data_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_keep_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_strb_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_user_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_last_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_id_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'v_tpg/m_axis_video_V_dest_V' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on function 'v_tpg' to 's_axilite & ap_ctrl_hs'. INFO: [RTGEN 206-100] Bundling port 'height', 'width', 'bckgndId', 'ovrlayId', 'maskId', 'motionSpeed', 'colorFormat', 'crossHairX', 'crossHairY', 'ZplateHorContStart', 'ZplateHorContDelta', 'ZplateVerContStart', 'ZplateVerContDelta', 'boxSize', 'boxColorR', 'boxColorG', 'boxColorB', 'dpDynamicRange', 'dpYUVCoef' and 'return' to AXI-Lite port CTRL. WARNING: [RTGEN 206-101] No memory core is bound to array [p_str10435]. INFO: [RTGEN 206-100] Finished creating RTL model for 'v_tpg'. INFO: [HLS 200-111] Elapsed time: 3.77 seconds; current allocated memory: 1.129 GB. INFO: [WVHDL 200-304] Encrypting RTL VHDL done. INFO: [WVHDL 200-304] Encrypting RTL Verilog done. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorbkb_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorcud_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColordEe_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColoreOg_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorfYi_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorg8j_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorhbi_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColoribs_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorjbC_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorkbM_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorlbW_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColormb6_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternDPColorncg_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCheckerocq_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCheckerqcK_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCheckersc4_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCheckertde_rom' using distributed ROMs. INFO: [RTMG 210-282] Generating pipelined core: 'design_1_v_tpg_0_1_v_tpg_mul_8ns_8s_wdI_Mul3S_0' INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternRainbowvdy_rom' using block ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCrossHaDeQ_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCrossHaEe0_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternTartanCFfa_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternZonePlaMgi_rom' using auto ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternSolidBlZio_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternSolidGr0iy_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternSolidRe1iI_rom' using distributed ROMs. INFO: [RTMG 210-279] Implementing memory 'design_1_v_tpg_0_1_tpgPatternCrossHa2iS_rom' using distributed ROMs. INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:03:22 ; elapsed = 00:06:27 . Memory (MB): peak = 1239.773 ; gain = 1187.660 INFO: [SYSC 207-301] Generating SystemC RTL for v_tpg with prefix design_1_v_tpg_0_1_. INFO: [VHDL 208-304] Generating VHDL RTL for v_tpg with prefix design_1_v_tpg_0_1_. INFO: [VLOG 209-307] Generating Verilog RTL for v_tpg with prefix design_1_v_tpg_0_1_. INFO: [IMPL 213-8] Exporting RTL as an IP in IP-XACT. ****** Vivado v2017.1 (64-bit) **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017 **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source run_ippack.tcl -notrace bad lexical cast: source type value could not be interpreted as target while executing "rdi::set_property core_revision 2202091317 {component component_1}" invoked from within "set_property core_revision $Revision $core" (file "run_ippack.tcl" line 861) INFO: [Common 17-206] Exiting Vivado at Wed Feb 9 13:17:51 2022... ERROR: [IMPL 213-28] Failed to generate IP. command 'ap_source' returned error code while executing "source [lindex $::argv 1] " ("uplevel" body line 1) invoked from within "uplevel \#0 { source [lindex $::argv 1] } " INFO: [HLS 200-112] Total elapsed time: 395.117 seconds; peak allocated memory: 1.129 GB. compile_c: Time (s): cpu = 00:00:02 ; elapsed = 00:06:37 . Memory (MB): peak = 1259.113 ; gain = 0.000