-------------------------------------------------------------------------------- Version 18.0 614 Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information is expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Welcome to Intel's FPGA System Console This Tcl console provides access to the hardware modules instantiated in your FPGA. You can use System Console for all of the following purposes: * To start, stop, or step a Nios II processor * To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters * To sample the SOPC system clock as well as system reset signal * To run JTAG loopback tests to analyze board noise problems * To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes In addition, the directory /sopc_builder/system_console/scripts contains Tcl files that provide miscellaneous utilities and examples of how to access the functionality provided. You can include those macros in your scripts by issuing Tcl source commands. -------------------------------------------------------------------------------- % source sc_tcl/main.tcl TEST_ETHERNET 10M MAC_LOOP_ENA = 0 PHY_ENABLE_AN = 0 PHY_LOOPBACK = 0 ============================================================================== Starting DP83867IS PHY Configuration System Console ============================================================================== Info: Opened JTAG Master Service Info: Configure On Board Ethernet PHY Chip =============================================== PHY read PHY Identifier Register 1 = 0x00002000 PHY read PHY Identifier Register 2 = 0x0000a231 =============================================== Configure PHY (MDIO ADDR = 0x00) PHY Global Software Reset(Resets PHY and Registers) PHY Global Software Reset Complete Set PHY SPEED to 10Mbps Disable PHY Auto-Negotiation Enable PHY In Full Duplex Mode PHY write Control Register = 0x100 PHY Software Reset(don't reset Registers) PHY Software Reset Complete PHY read Control Register = 0x00000100 =============================================== Advertise PHY 10BASE-TX Full Duplex PHY write AN Advertisement Register = 0x41 PHY Software Reset(don't reset Registers) PHY Software Reset Complete PHY read AN Advertisement Register = 0x00000041 =============================================== PHY write 1000BASE-T Control Register = 0x0 PHY Software Reset(don't reset Registers) PHY Software Reset Complete PHY read 1000BASE-T Control Register = 0x00000000 PHY read 1000BASE-T Status Register = 0x00000000 =============================================== Set PHY Synchronizing FIFO TX to maximum PHY write Specific Control Address = 0xd048 PHY Software Reset(don't reset Registers) PHY Software Reset Complete PHY read Specific Control Address = 0x0000d048 =============================================== PHY READ RGMII Control Register Address = 0x000000d3 PHY write RGMII Control Register Address = 0xd3 PHY READ RGMII Control Register Address = 0x000000d3 PHY Software Reset(don't reset Registers) PHY Software Reset Complete PHY READ RGMII Control Register Address = 0x000000d3 =============================================== !!! PHY Link Up !!! PHY Speed and Duplex Resolved. PHY operating in Full Duplex mode. PHY operating Speed 10Mbps ++++++++++++++++++ END INIT PHY ++++++++++++++++++++++++++ PHY_CONTROL_ADDRESS (REG0 0x0) = 0x00000100 PHY_STATUS_ADDRESS (REG1 0x1) = 0x0000794d PHY_IDENT_REG1_ADDRESS (REG2 0x2) = 0x00002000 PHY_IDENT_REG2_ADDRESS (REG3 0x3) = 0x0000a231 PHY_AUTO_NEG_ADDRESS (REG4 0x4) = 0x00000041 PHY_1000BASE_T_CONTROL_ADDRESS (REG9 0x9) = 0x00000000 PHY_1000BASE_T_STATUS_ADDRESS (REG10 0xA) = 0x00000000 PHY_SPECIFIC_CONTROL_ADDRESS (REG16 0x10) = 0x0000d048 PHY_SPECIFIC_STATUS_ADDRESS (REG17 0x11) = 0x00002c02 PHY_RGMII_CONTROL_ADDRESS (REG50 0x32) = 0x000000d3 Info: Closed JTAG Master Service ============================================================================== Starting TSE MAC Configuration System Console ============================================================================== Info: Opened JTAG Master Service Info: Address AVL_ETH_CTRL = 0x808000 Info: Configure TSE MAC TSE MAC Rev = 0x00001200 TSE MAC write Scratch = 0xabcd0123 TSE MAC read Scratch = 0xabcd0123 MAC Software Reset and Disable RX & TX Command Config Under Reset = 0x00000000 MAC Software Reset Complete Command Config After Reset = 0x00000000 Write MAC Address 0 = 0x44332211 Write MAC Address 1 = 0x6655 Write Frame Length = 0x5ee Write Pause Quanta = 0x2000 Write RX Section Empty = 0x1fec Write RX Section Full = 0x10 Write TX Section Empty = 0x1fec Write TX Section Full = 0x10 Write RX Almost Empty = 0x8 Write RX Almost Full = 0x8 Write TX Almost Empty = 0x8 Write TX Almost Full = 0x3 Write TX IPG Length = 0xc Write TX Command Status = 0x20000 Write RX Command Status = 0x0 MAC Software Reset and Enable RX & TX MAC Software Reset Complete Write Command Config = 0x2000033 Command Config After Reset = 0x02000033 MAC Address 0 = 0x44332211 MAC Address 1 = 0x00006655 Frame Length = 0x000005ee Pause Quanta = 0x00002000 RX Section Empty = 0x000007ec RX Section Full = 0x00000010 TX Section Empty = 0x000007ec TX Section Full = 0x00000010 RX Almost Empty = 0x00000008 RX Almost Full = 0x00000008 TX Almost Empty = 0x00000008 TX Almost Full = 0x00000003 TX IPG Length = 0x0000000c TX Command Status = 0x00020000 RX Command Status = 0x00000000 Info: Closed JTAG Master Service ============================================================================== Starting Ethernet Generator FROM FILE sc_tcl/test_packet.txt ============================================================================== Info: Opened JTAG Master Service Read Files sc_tcl/test_packet.txt 503eaa0415f711223344556608004500002112340100ff112738c0a80005c0a8000a1f9022b8000d3cd6aaaaaaaaaa00000000000000000000000000 Ethernet Frame: 0x50 0x3e 0xaa 0x4 0x15 0xf7 0x11 0x22 0x33 0x44 0x55 0x66 0x8 0x0 0x45 0x0 0x0 0x21 0x12 0x34 0x1 0x0 0xff 0x11 0x27 0x38 0xc0 0xa8 0x0 0x5 0xc0 0xa8 0x0 0xa 0x1f 0x90 0x22 0xb8 0x0 0xd 0x3c 0xd6 0xaa 0xaa 0xaa 0xaa 0xaa 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 =============================================== Start DMA from Memory to Ethernet: AVL_ETH_DMA_TX_CSR = 0x808420 AVL_ETH_DMA_TX_DESC = 0x808400 ETH_DMA_DESC_CTRL = 0x80000300 Send Packet №0 of 2 AVL_ETH_CTRL COMMAND CONFIG Reg = 0x02000033 AVL_ETH_DMA_TX_CSR_STATUS = 0x00000002 AVL_ETH_DMA_TX_CSR_CTRL = 0x00000000 Send Packet №1 of 2 AVL_ETH_CTRL COMMAND CONFIG Reg = 0x02000033 AVL_ETH_DMA_TX_CSR_STATUS = 0x00000002 AVL_ETH_DMA_TX_CSR_CTRL = 0x00000000 Info: Closed JTAG Master Service ============================================================================== TSE MAC Statistics Counters Map ============================================================================== Info: Opened JTAG Master Service Addr Name Read Value ---- ---- ---------- 0x808060 aMacID0 1144201745 0x808064 aMacID1 26197 0x808068 aFramesTransmittedOK 2 0x80806c aFramesReceivedOK 0 0x808070 aFrameCheckSequenceErrors 0 0x808074 aAlignmentErrors 0 0x808078 aOctetsTransmittedOK 84 0x80807c aOctetsReceivedOK 0 0x808080 aTxPAUSEMACCtrlFrames 0 0x808084 aRxPAUSEMACCtrlFrames 0 0x808088 ifInErrors 0 0x80808c ifOutErrors 0 0x808090 ifInUcastPkts 0 0x808094 ifInMulticastPkts 0 0x808098 ifInBroadcastPkts 0 0x80809c ifOutDiscards 0 0x8080a0 ifOutUcastPkts 2 0x8080a4 ifOutMulticastPkts 0 0x8080a8 ifOutBroadcastPkts 0 0x8080ac etherStatsDropEvents 0 0x8080b0 etherStatsOctets 0 0x8080b4 etherStatsPkts 0 0x8080b8 etherStatsUndersizePkts 0 0x8080bc etherStatsOversizePkts 0 0x8080c0 etherStatsPkts64Octets 0 0x8080c4 etherStatsPkts65to127Octets 0 0x8080c8 etherStatsPkts128to255Octets 0 0x8080cc etherStatsPkts256to511Octets 0 0x8080d0 etherStatsPkts512to1023Octets 0 0x8080d4 etherStatsPkts1024to1518Octets 0 0x8080d8 etherStatsPkts1519toXOctets 0 0x8080dc etherStatsJabbers 0 0x8080e0 etherStatsFragments 0 Info: Closed JTAG Master Service %