## Generated SDC file "test_sdram.out.sdc" ## Copyright (C) 1991-2016 Altera Corporation. All rights reserved. ## Your use of Altera Corporation's design tools, logic functions ## and other software and tools, and its AMPP partner logic ## functions, and any output files from any of the foregoing ## (including device programming or simulation files), and any ## associated documentation or information are expressly subject ## to the terms and conditions of the Altera Program License ## Subscription Agreement, the Altera Quartus Prime License Agreement, ## the Altera MegaCore Function License Agreement, or other ## applicable license agreement, including, without limitation, ## that your use is for the sole purpose of programming logic ## devices manufactured by Altera and sold by Altera or its ## authorized distributors. Please refer to the applicable ## agreement for further details. ## VENDOR "Altera" ## PROGRAM "Quartus Prime" ## VERSION "Version 15.1.2 Build 193 02/01/2016 SJ Standard Edition" ## DATE "Mon Apr 22 16:19:44 2019" ## ## DEVICE "10M50SAE144I7G" ## #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 set SDRAM_A0_delay_max [expr 20.292*0.007+0.1] set SDRAM_A1_delay_max [expr 19.416*0.007+0.1] set SDRAM_A2_delay_max [expr 18.552*0.007+0.1] set SDRAM_A3_delay_max [expr 17.683*0.007+0.1] set SDRAM_A4_delay_max [expr 16.79*0.007+0.1] set SDRAM_A5_delay_max [expr 19.61*0.007+0.1] set SDRAM_A6_delay_max [expr 21.408*0.007+0.1] set SDRAM_A7_delay_max [expr 21.847*0.007+0.1] set SDRAM_A8_delay_max [expr 23.728*0.007+0.1] set SDRAM_A9_delay_max [expr 23.273*0.007+0.1] set SDRAM_A10_delay_max [expr 21.411*0.007+0.1] set SDRAM_A11_delay_max [expr 24.184*0.007+0.1] set SDRAM_A12_delay_max [expr 25.255*0.007+0.1] set SDRAM_BA0_delay_max [expr 23.822*0.007+0.1] set SDRAM_BA1_delay_max [expr 22.885*0.007+0.1] set SDRAM_CAS_N_delay_max [expr 30.654*0.007+0.1] set SDRAM_DQ0_delay_max [expr 53.461*0.007+0.1] set SDRAM_DQ1_delay_max [expr 43.258*0.007+0.1] set SDRAM_DQ2_delay_max [expr 41.535*0.007+0.1] set SDRAM_DQ3_delay_max [expr 39.165*0.007+0.1] set SDRAM_DQ4_delay_max [expr 37.297*0.007+0.1] set SDRAM_DQ5_delay_max [expr 31.949*0.007+0.1] set SDRAM_DQ6_delay_max [expr 39.624*0.007+0.1] set SDRAM_DQ7_delay_max [expr 30.029*0.007+0.1] set SDRAM_DQ8_delay_max [expr 27.938*0.007+0.1] set SDRAM_DQ9_delay_max [expr 40.647*0.007+0.1] set SDRAM_DQ10_delay_max [expr 42.304*0.007+0.1] set SDRAM_DQ11_delay_max [expr 45.101*0.007+0.1] set SDRAM_DQ12_delay_max [expr 46.758*0.007+0.1] set SDRAM_DQ13_delay_max [expr 49.436*0.007+0.1] set SDRAM_DQ14_delay_max [expr 51.598*0.007+0.1] set SDRAM_DQ15_delay_max [expr 55.733*0.007+0.1] set SDRAM_DQMH_delay_max [expr 25.126*0.007+0.1] set SDRAM_DQML_delay_max [expr 28.175*0.007+0.1] set SDRAM_RAS_N_delay_max [expr 26.992*0.007+0.1] set SDRAM_WE_N_delay_max [expr 31.134*0.007+0.1] set SDRAM_CLK_delay_max [expr 24.044*0.007+0.1] set tAC 5.4 set tSU 1.5 set SDRAM_A0_delay_min [expr 20.292*0.007-0.1] set SDRAM_A1_delay_min [expr 19.416*0.007-0.1] set SDRAM_A2_delay_min [expr 18.552*0.007-0.1] set SDRAM_A3_delay_min [expr 17.683*0.007-0.1] set SDRAM_A4_delay_min [expr 16.79*0.007-0.1] set SDRAM_A5_delay_min [expr 19.61*0.007-0.1] set SDRAM_A6_delay_min [expr 21.408*0.007-0.1] set SDRAM_A7_delay_min [expr 21.847*0.007-0.1] set SDRAM_A8_delay_min [expr 23.728*0.007-0.1] set SDRAM_A9_delay_min [expr 23.273*0.007-0.1] set SDRAM_A10_delay_min [expr 21.411*0.007-0.1] set SDRAM_A11_delay_min [expr 24.184*0.007-0.1] set SDRAM_A12_delay_min [expr 25.255*0.007-0.1] set SDRAM_BA0_delay_min [expr 23.822*0.007-0.1] set SDRAM_BA1_delay_min [expr 22.885*0.007-0.1] set SDRAM_CAS_N_delay_min [expr 30.654*0.007-0.1] set SDRAM_DQ0_delay_min [expr 53.461*0.007-0.1] set SDRAM_DQ1_delay_min [expr 43.258*0.007-0.1] set SDRAM_DQ2_delay_min [expr 41.535*0.007-0.1] set SDRAM_DQ3_delay_min [expr 39.165*0.007-0.1] set SDRAM_DQ4_delay_min [expr 37.297*0.007-0.1] set SDRAM_DQ5_delay_min [expr 31.949*0.007-0.1] set SDRAM_DQ6_delay_min [expr 39.624*0.007-0.1] set SDRAM_DQ7_delay_min [expr 30.029*0.007-0.1] set SDRAM_DQ8_delay_min [expr 27.938*0.007-0.1] set SDRAM_DQ9_delay_min [expr 40.647*0.007-0.1] set SDRAM_DQ10_delay_min [expr 42.304*0.007-0.1] set SDRAM_DQ11_delay_min [expr 45.101*0.007-0.1] set SDRAM_DQ12_delay_min [expr 46.758*0.007-0.1] set SDRAM_DQ13_delay_min [expr 49.436*0.007-0.1] set SDRAM_DQ14_delay_min [expr 51.598*0.007-0.1] set SDRAM_DQ15_delay_min [expr 55.733*0.007-0.1] set SDRAM_DQMH_delay_min [expr 25.126*0.007-0.1] set SDRAM_DQML_delay_min [expr 28.175*0.007-0.1] set SDRAM_RAS_N_delay_min [expr 26.992*0.007-0.1] set SDRAM_WE_N_delay_min [expr 31.134*0.007-0.1] set SDRAM_CLK_delay_min [expr 24.044*0.007-0.1] set tOH 3 set tH 0.8 #************************************************************** # Create Clock #************************************************************** derive_pll_clocks derive_clock_uncertainty create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] create_clock -name {inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc} -period 181.818 -waveform { 0.000 90.909 } [get_pins {inst|onchip_flash|altera_onchip_flash_block|ufm_block|osc}] create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}] #************************************************************** # Create Generated Clock #************************************************************** #************************************************************** # Set Clock Latency #************************************************************** #************************************************************** # Set Clock Uncertainty #************************************************************** #************************************************************** # Set Input Delay #************************************************************** set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ0_delay_max ] [get_ports {SDRAM_DQ[0]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ1_delay_max ] [get_ports {SDRAM_DQ[1]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ2_delay_max ] [get_ports {SDRAM_DQ[2]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ3_delay_max ] [get_ports {SDRAM_DQ[3]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ4_delay_max ] [get_ports {SDRAM_DQ[4]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ5_delay_max ] [get_ports {SDRAM_DQ[5]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ6_delay_max ] [get_ports {SDRAM_DQ[6]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ7_delay_max ] [get_ports {SDRAM_DQ[7]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ8_delay_max ] [get_ports {SDRAM_DQ[8]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ9_delay_max ] [get_ports {SDRAM_DQ[9]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ10_delay_max ] [get_ports {SDRAM_DQ[10]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ11_delay_max ] [get_ports {SDRAM_DQ[11]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ12_delay_max ] [get_ports {SDRAM_DQ[12]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ13_delay_max ] [get_ports {SDRAM_DQ[13]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ14_delay_max ] [get_ports {SDRAM_DQ[14]}] set_input_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tAC + $SDRAM_DQ15_delay_max ] [get_ports {SDRAM_DQ[15]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ0_delay_min ] [get_ports {SDRAM_DQ[0]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ1_delay_min ] [get_ports {SDRAM_DQ[1]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ2_delay_min ] [get_ports {SDRAM_DQ[2]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ3_delay_min ] [get_ports {SDRAM_DQ[3]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ4_delay_min ] [get_ports {SDRAM_DQ[4]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ5_delay_min ] [get_ports {SDRAM_DQ[5]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ6_delay_min ] [get_ports {SDRAM_DQ[6]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ7_delay_min ] [get_ports {SDRAM_DQ[7]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ8_delay_min ] [get_ports {SDRAM_DQ[8]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ9_delay_min ] [get_ports {SDRAM_DQ[9]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ10_delay_min ] [get_ports {SDRAM_DQ[10]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ11_delay_min ] [get_ports {SDRAM_DQ[11]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ12_delay_min ] [get_ports {SDRAM_DQ[12]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ13_delay_min ] [get_ports {SDRAM_DQ[13]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ14_delay_min ] [get_ports {SDRAM_DQ[14]}] set_input_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tOH + $SDRAM_DQ15_delay_min ] [get_ports {SDRAM_DQ[15]}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ0_delay_max ] [get_ports {SDRAM_DQ[0]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ1_delay_max ] [get_ports {SDRAM_DQ[1]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ2_delay_max ] [get_ports {SDRAM_DQ[2]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ3_delay_max ] [get_ports {SDRAM_DQ[3]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ4_delay_max ] [get_ports {SDRAM_DQ[4]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ5_delay_max ] [get_ports {SDRAM_DQ[5]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ6_delay_max ] [get_ports {SDRAM_DQ[6]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ7_delay_max ] [get_ports {SDRAM_DQ[7]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ8_delay_max ] [get_ports {SDRAM_DQ[8]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ9_delay_max ] [get_ports {SDRAM_DQ[9]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ10_delay_max ] [get_ports {SDRAM_DQ[10]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ11_delay_max ] [get_ports {SDRAM_DQ[11]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ12_delay_max ] [get_ports {SDRAM_DQ[12]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ13_delay_max ] [get_ports {SDRAM_DQ[13]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ14_delay_max ] [get_ports {SDRAM_DQ[14]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQ15_delay_max ] [get_ports {SDRAM_DQ[15]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A0_delay_max ] [get_ports {SDRAM_ADDR[0]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A1_delay_max ] [get_ports {SDRAM_ADDR[1]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A2_delay_max ] [get_ports {SDRAM_ADDR[2]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A3_delay_max ] [get_ports {SDRAM_ADDR[3]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A4_delay_max ] [get_ports {SDRAM_ADDR[4]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A5_delay_max ] [get_ports {SDRAM_ADDR[5]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A6_delay_max ] [get_ports {SDRAM_ADDR[6]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A7_delay_max ] [get_ports {SDRAM_ADDR[7]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A8_delay_max ] [get_ports {SDRAM_ADDR[8]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A9_delay_max ] [get_ports {SDRAM_ADDR[9]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A10_delay_max ] [get_ports {SDRAM_ADDR[10]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A11_delay_max ] [get_ports {SDRAM_ADDR[11]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_A12_delay_max ] [get_ports {SDRAM_ADDR[12]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_BA0_delay_max ] [get_ports {SDRAM_BA[0]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_BA1_delay_max ] [get_ports {SDRAM_BA[1]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQMH_delay_max ] [get_ports {SDRAM_DQM[1]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_DQML_delay_max ] [get_ports {SDRAM_DQM[0]}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_CAS_N_delay_max ] [get_ports {SDRAM_CAS}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_RAS_N_delay_max ] [get_ports {SDRAM_RAS}] set_output_delay -max -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_max + $tSU + $SDRAM_WE_N_delay_max ] [get_ports {SDRAM_WE}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ0_delay_min ] [get_ports {SDRAM_DQ[0]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ1_delay_min ] [get_ports {SDRAM_DQ[1]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ2_delay_min ] [get_ports {SDRAM_DQ[2]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ3_delay_min ] [get_ports {SDRAM_DQ[3]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ4_delay_min ] [get_ports {SDRAM_DQ[4]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ5_delay_min ] [get_ports {SDRAM_DQ[5]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ6_delay_min ] [get_ports {SDRAM_DQ[6]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ7_delay_min ] [get_ports {SDRAM_DQ[7]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ8_delay_min ] [get_ports {SDRAM_DQ[8]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ9_delay_min ] [get_ports {SDRAM_DQ[9]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ10_delay_min ] [get_ports {SDRAM_DQ[10]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ11_delay_min ] [get_ports {SDRAM_DQ[11]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ12_delay_min ] [get_ports {SDRAM_DQ[12]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ13_delay_min ] [get_ports {SDRAM_DQ[13]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ14_delay_min ] [get_ports {SDRAM_DQ[14]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQ15_delay_min ] [get_ports {SDRAM_DQ[15]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A0_delay_min ] [get_ports {SDRAM_ADDR[0]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A1_delay_min ] [get_ports {SDRAM_ADDR[1]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A2_delay_min ] [get_ports {SDRAM_ADDR[2]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A3_delay_min ] [get_ports {SDRAM_ADDR[3]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A4_delay_min ] [get_ports {SDRAM_ADDR[4]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A5_delay_min ] [get_ports {SDRAM_ADDR[5]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A6_delay_min ] [get_ports {SDRAM_ADDR[6]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A7_delay_min ] [get_ports {SDRAM_ADDR[7]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A8_delay_min ] [get_ports {SDRAM_ADDR[8]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A9_delay_min ] [get_ports {SDRAM_ADDR[9]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A10_delay_min ] [get_ports {SDRAM_ADDR[10]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A11_delay_min ] [get_ports {SDRAM_ADDR[11]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_A12_delay_min ] [get_ports {SDRAM_ADDR[12]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_BA0_delay_min ] [get_ports {SDRAM_BA[0]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_BA1_delay_min ] [get_ports {SDRAM_BA[1]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQMH_delay_min ] [get_ports {SDRAM_DQM[1]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_DQML_delay_min ] [get_ports {SDRAM_DQM[0]}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_CAS_N_delay_min ] [get_ports {SDRAM_CAS}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_RAS_N_delay_min ] [get_ports {SDRAM_RAS}] set_output_delay -min -clock [get_clocks {inst|altpll|sd1|pll7|clk[1]}] [expr $SDRAM_CLK_delay_min + $tH + $SDRAM_WE_N_delay_min ] [get_ports {SDRAM_WE}] #************************************************************** # Set Clock Groups #************************************************************** set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] #set_clock_groups -exclusive -group [get_clocks {inst3|altpll|sd1|pll7|clk[0]}] -group [get_clocks {inst3|altpll|sd1|pll7|clk[1]}] #************************************************************** # Set False Path #************************************************************** set_false_path -from [get_ports {DEBUG_USB_UART_RXD}] -to [all_clocks] set_false_path -from [all_clocks] -to [get_ports {DEBUG_USB_UART_TXD}] set_false_path -from [all_clocks] -to [get_ports {Test_LED0}] set_false_path -from [all_clocks] -to [get_ports {Test_LED1}] set_false_path -from [all_clocks] -to [get_ports {SDRAM_CKE}] set_false_path -from [all_clocks] -to [get_ports {SDRAM_CS}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}] set_false_path -to [get_registers {*|flash_busy_reg}] set_false_path -to [get_registers {*|flash_busy_clear_reg}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_oci_break:the_system_cpu_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr*}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_oci_debug:the_system_cpu_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr[33]}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_oci_debug:the_system_cpu_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr[0]}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_oci_debug:the_system_cpu_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr[34]}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_ocimem:the_system_cpu_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr*}] set_false_path -from [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_tck:the_system_cpu_cpu_debug_slave_tck|*sr*}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_sysclk:the_system_cpu_cpu_debug_slave_sysclk|*jdo*}] set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_debug_slave_wrapper:the_system_cpu_cpu_debug_slave_wrapper|system_cpu_cpu_debug_slave_sysclk:the_system_cpu_cpu_debug_slave_sysclk|ir*}] set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*system_cpu_cpu:*|system_cpu_cpu_nios2_oci:the_system_cpu_cpu_nios2_oci|system_cpu_cpu_nios2_oci_debug:the_system_cpu_cpu_nios2_oci_debug|monitor_go}] #************************************************************** # Set Multicycle Path #************************************************************** #************************************************************** # Set Maximum Delay #************************************************************** set_max_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] 100.000 set_max_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] 100.000 #************************************************************** # Set Minimum Delay #************************************************************** set_min_delay -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}] -100.000 set_min_delay -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] -100.000 #************************************************************** # Set Input Transition #************************************************************** #************************************************************** # Set Net Delay #************************************************************** set_net_delay -max 2.000 -from [get_registers *] -to [get_registers {*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:*|din_s1}] set_net_delay -max 2.000 -from [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}] -to [get_registers {*altera_avalon_st_clock_crosser:*|out_data_buffer*}]