//------------------------------------------------------------------------------
//
// Design unit generated by Aldec IP Core Generator, version 10.4.
// Copyright (c) 1997 - 2016 by Aldec, Inc. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Created on Wednesday 2018-12-05, 15:36:27
//
//------------------------------------------------------------------------------
// Details:
//		Type: Cascadable Accumulator with Adder
//		Data width: 6
//		Clock input CLK active high
//		Asynchronous Clear input CLR active : high
//------------------------------------------------------------------------------

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {generator_acc6}}

module generator_acc6 (CLK, CLR, A, Q);

	input  CLK;
	input  CLR;
	input  [5:0] A;
	output [5:0] Q;

//}} End of automatically maintained section

	reg  [5:0] Q_REG;
	reg  [5:0] Q_TEMP;

	always @(Q_REG or A)
	begin

		Q_TEMP  = Q_REG  + A ;

	end

	always @(posedge CLK or posedge CLR)
	begin

		if (CLR  ==  1)
			Q_REG = {6{1'b0}};
		else
			Q_REG  = Q_TEMP;

	end

	assign Q  = Q_REG;


endmodule
//------------------------------------------------------------------------------
//
// Design unit generated by Aldec IP Core Generator, version 10.4.
// Copyright (c) 1997 - 2016 by Aldec, Inc. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Created on Wednesday 2018-12-05, 15:36:27
//
//------------------------------------------------------------------------------
// Details:
//		Type: Analog generator ROM block
//------------------------------------------------------------------------------

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {generator_sin}}

module generator_sin (Q, ADDRESS);
	input [5:0]ADDRESS;
	output [7:0] Q;
	reg [7:0] Q;

//}} End of automatically maintained section

	always @(ADDRESS)
	begin
		case (ADDRESS) 
			0  : Q = 128;
			1  : Q = 140;
			2  : Q = 152;
			3  : Q = 165;
			4  : Q = 176;
			5  : Q = 188;
			6  : Q = 198;
			7  : Q = 208;
			8  : Q = 218;
			9  : Q = 226;
			10 : Q = 234;
			11 : Q = 240;
			12 : Q = 245;
			13 : Q = 250;
			14 : Q = 253;
			15 : Q = 254;
			16 : Q = 255;
			17 : Q = 254;
			18 : Q = 253;
			19 : Q = 250;
			20 : Q = 245;
			21 : Q = 240;
			22 : Q = 234;
			23 : Q = 226;
			24 : Q = 218;
			25 : Q = 208;
			26 : Q = 198;
			27 : Q = 188;
			28 : Q = 176;
			29 : Q = 165;
			30 : Q = 152;
			31 : Q = 140;
			32 : Q = 127;
			33 : Q = 115;
			34 : Q = 103;
			35 : Q = 90;
			36 : Q = 79;
			37 : Q = 67;
			38 : Q = 57;
			39 : Q = 47;
			40 : Q = 37;
			41 : Q = 29;
			42 : Q = 21;
			43 : Q = 15;
			44 : Q = 10;
			45 : Q = 5;
			46 : Q = 2;
			47 : Q = 1;
			48 : Q = 0;
			49 : Q = 1;
			50 : Q = 2;
			51 : Q = 5;
			52 : Q = 10;
			53 : Q = 15;
			54 : Q = 21;
			55 : Q = 29;
			56 : Q = 37;
			57 : Q = 47;
			58 : Q = 57;
			59 : Q = 67;
			60 : Q = 79;
			61 : Q = 90;
			62 : Q = 103;
			63 : Q = 115;
		default : Q = 8'b00000000;
		endcase
	end
endmodule
//------------------------------------------------------------------------------
//
// Design unit generated by Aldec IP Core Generator, version 10.4.
// Copyright (c) 1997 - 2016 by Aldec, Inc. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Created on Wednesday 2018-12-05, 15:36:27
//
//------------------------------------------------------------------------------
// Details: 
//		Type: D type flip-flop register
//		Data width: 6
//		Clock input CLK active high
//		Clock enable input CE active high
//		Asynchronous clear input CLR active high
//------------------------------------------------------------------------------

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {generator_reg6}}

module generator_reg6 (CLR, CE, CLK, DATA, Q);

input CLR;
input CE;
input CLK;
input [5:0] DATA;
output [5:0] Q;
reg [5:0] Q;

//}} End of automatically maintained section

	always @(posedge CLR or posedge CLK)
		if (CLR == 1'b1)
			Q = {6{1'b0}};
		else if (CE == 1'b1)
				Q = DATA;

endmodule
//------------------------------------------------------------------------------
//
// Design unit generated by Aldec IP Core Generator, version 10.4.
// Copyright (c) 1997 - 2016 by Aldec, Inc. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Created on Wednesday 2018-12-05, 15:36:27
//
//------------------------------------------------------------------------------
// Details: 
//		Type: D type flip-flop register
//		Data width: 8
//		Clock input CLK active high
//		Asynchronous clear input CLR active high
//------------------------------------------------------------------------------

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {generator_reg8}}

module generator_reg8 (CLR, CLK, DATA, Q);

input CLR;
input CLK;
input [7:0] DATA;
output [7:0] Q;
reg [7:0] Q;

//}} End of automatically maintained section

	always @(posedge CLR or posedge CLK)
		if (CLR == 1'b1)
			Q = {8{1'b0}};
		else
			Q = DATA;

endmodule
//------------------------------------------------------------------------------
//
// Design unit generated by Aldec IP Core Generator, version 10.4.
// Copyright (c) 1997 - 2016 by Aldec, Inc. All rights reserved.
//
//------------------------------------------------------------------------------
//
// Created on Wednesday 2018-12-05, 15:36:27
//
//------------------------------------------------------------------------------
// Details:
//		Type: Analog generator
//------------------------------------------------------------------------------

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {generator}}

module generator (Q, DATA, FR, CLR, CLK);

input FR;
input CLR;
input CLK;
output [7:0] Q;
input [5:0] DATA;

//}} End of automatically maintained section

wire CE_FR;
wire [5:0] cur_FR;
wire [5:0] def_FR;
wire [7:0] VAL;

	generator_reg6 U1(
		.CE(FR),
		.CLK(CLK),
		.CLR(CLR),
		.DATA(DATA),
		.Q(def_FR));

	generator_acc6 U2(
		.A(def_FR),
		.CLR(CLR ),
		.CLK(CLK ),
		.Q(cur_FR ));

	generator_sin U3(
		.ADDRESS(cur_FR ),
		.Q(VAL ));

	generator_reg8 U4(
		.CLR(CLR),
		.CLK(CLK),
		.DATA(VAL),
		.Q(Q));


endmodule