Signals handled by operating system
Stopping running target Altera - Cyclone V SoC (Dual Core) on connection
Connected to running target Altera - Cyclone V SoC (Dual Core)
Execution stopped in SVC mode at S:0x00002FA8
On core Cortex-A9_0 (ID 0)
S:0x00002FA8   TST      r1,#4
cd "D:\DS-5 Workspace"
Working directory "D:\DS-5 Workspace"
Execution stopped in SVC mode at S:0x00002FA8
On core Cortex-A9_0 (ID 0)
source /v "C:\Program Files\DS-5 v5.28.0\sw\debugger\configdb\Scripts\altera_target_check.py"
S:0x00002FA8   TST      r1,#4

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "D:\Micrium\Examples\Altera\CycloneV-SOC-DevKit\BSP\ARM_Compiler\preloader.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+set semihosting enabled 1
Semihosting server socket created at port 8017
WARNING(TAB139): Semihosting was enabled after the target had started running so may not work correctly. Enable semihosting in a target initialization debugger script or with an image symbol instead
+loadfile "$sdir/../u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF614F (size 0x6150)
Loaded section .rodata: S:0xFFFF6150 ~ S:0xFFFF7752 (size 0x1603)
Loaded section .data: S:0xFFFF7758 ~ S:0xFFFF85C7 (size 0xE70)
Entry point S:0xFFFF0000
WARNING(ROS68): OS support has been disabled due to a system reset. Support will not be re-enabled automatically by the debugger, it can be done manually when the system has been brought back to an appropriate state.
Target has been reset
WARNING(ROS68): OS support has been disabled due to a system reset. Support will not be re-enabled automatically by the debugger, it can be done manually when the system has been brought back to an appropriate state.
Target has been reset
Execution stopped in SVC mode at S:0x00000000
On core Cortex-A9_0 (ID 0)
In image_get_data (no debug info)
S:0x00000000   LDR      pc,[pc,#24] ; [0x20] = 0xA8
+set debug-from *$entrypoint     # Set start-at setting to address of $entrypoint
+start 
Reloading program
Starting target with image D:\Micrium\Examples\Altera\CycloneV-SOC-DevKit\BSP\u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000
On core Cortex-A9_0 (ID 0)
In start.S
Unable to read source file C:/Altera/14.0/embedded/examples/hardware/cv_soc_devkit_ghrd/software/spl_bsp/uboot-socfpga/arch/arm/cpu/armv7/start.S
S:0xFFFF0000   39,0   B        reset ; 0xFFFF0070
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF0FBC
	on file spl.c, line 70
	on file spl.c, line 80
+cont
+wait 60s
loadfile "D:\Micrium\Examples\Altera\CycloneV-SOC-DevKit\OS3\ARM_DS-5\Debug\CycloneV-SOC-DevKit_OS3.axf"
ERROR(CMD16-TAD274-NAL33): 
! Failed to load "CycloneV-SOC-DevKit_OS3.axf"
! Failed to write 49 152 bytes to address N:0x01000000 while writing block of 4 096 bytes to address N:0x01000000
! Target is running, cannot access.
handle UNDEF stop
Signal Stop Print Description
UNDEF  Yes  Yes   Undefined Instruction
	Vector used by the debugger to provide support for semihosting
WARNING(CMD668): The signal UNDEF is also in use by the debugger
handle PREFETCH_ABORT stop
Signal         Stop Print Description
PREFETCH_ABORT Yes  Yes   Prefetch Abort
handle DATA_ABORT stop
Signal     Stop Print Description
DATA_ABORT Yes  Yes   Data Abort
handle FIQ stop
Signal Stop Print Description
FIQ    Yes  Yes   FIQ (fast interrupt)
handle SMC stop
Signal Stop Print Description
SMC    Yes  Yes   Secure Monitor Call (SMC)
handle MONITOR_PREFETCH_ABORT stop
Signal                 Stop Print Description
MONITOR_PREFETCH_ABORT Yes  Yes   Monitor Mode Prefetch Abort
handle MONITOR_DATA_ABORT stop
Signal             Stop Print Description
MONITOR_DATA_ABORT Yes  Yes   Monitor Mode Data Abort
handle MONITOR_FIQ stop
Signal      Stop Print Description
MONITOR_FIQ Yes  Yes   Monitor Mode FIQ (fast interrupt)
handle NON-SECURE_UNDEF stop
Signal           Stop Print Description
NON-SECURE_UNDEF Yes  Yes   Non-Secure Undefined Instruction
	Vector used by the debugger to provide support for semihosting
WARNING(CMD668): The signal NON-SECURE_UNDEF is also in use by the debugger
handle NON-SECURE_PREFETCH_ABORT stop
Signal                    Stop Print Description
NON-SECURE_PREFETCH_ABORT Yes  Yes   Non-Secure Prefetch Abort
handle NON-SECURE_DATA_ABORT stop
Signal                Stop Print Description
NON-SECURE_DATA_ABORT Yes  Yes   Non-Secure Data Abort
handle NON-SECURE_FIQ stop
Signal         Stop Print Description
NON-SECURE_FIQ Yes  Yes   Non-Secure FIQ (fast interrupt)
set debug-from main
start
ERROR(COR113): Unable to stop the device
wait