Vivado Simulator 2015.3
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2015.3/bin/unwrapped/win64.o/xelab.exe -wto bd712199ea274db5a9d04c8ebb47b6d7 --debug off --dll --relax --mt 2 -L xbip_utils_v3_0 -L fir_compiler_v7_2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot fir_compiler_v7_2_control_1e6971908165223f67a8b2bf6f4621c0_behav xil_defaultlib.fir_compiler_v7_2_control_1e6971908165223f67a8b2bf6f4621c0 xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
WARNING: [VRFC 10-975] left bound value <15> of slice is out of range [0:0] of array <s_axis_reload_tdata> [C:/Users/08A4~1/AppData/Local/Temp/xlsim59393e36/hdl_netlist/xelab.srcs/sources_1/imports/xlxsim59393e33/fir_compiler_v7_2_timing_model.vhd:2365]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "C:/Users/08A4~1/AppData/Local/Temp/xlsim59393e36/hdl_netlist/xelab.srcs/sources_1/imports/xlxsim59393e33/xlclockdriver_rd.v" Line 22. Module xlclockdriver(period=1,use_bufg=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "C:/Users/08A4~1/AppData/Local/Temp/xlsim59393e36/hdl_netlist/xelab.srcs/sources_1/imports/xlxsim59393e33/synth_reg_w_init.v" Line 3. Module synth_reg_w_init(width=1,init_value=1'b0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "C:/Users/08A4~1/AppData/Local/Temp/xlsim59393e36/hdl_netlist/xelab.srcs/sources_1/imports/xlxsim59393e33/synth_reg_w_init.v" Line 45. Module single_reg_w_init(width=1,init_index=0,init_value=1'b0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2015.3/nightly/2015_09_28_1368829/data/verilog/src/unisims/FDRE.v" Line 175. Module FDRE has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2015.3/nightly/2015_09_28_1368829/data/verilog/src/unisims/FDRE.v" Line 25. Module sffsrce_fdre has a timescale but at least one module in design doesn't have timescale.
ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.