# This is a generated script based on design: zynq_system
#
# Though there are limitaions about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
#
# To test this script, run the following commands from Vivado Tcl console:
# source zynq_system_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
 create_project zynq_system zynqbfmsystem -part xc7z020clg484-1 -force

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
create_bd_design zynq_system

# Creating design if needed
if { [get_files *.bd] eq "" } {
   puts "INFO: Currently there are no designs in project, so creating one..."
   create_bd_design zynq_system
}


# Top level instance
current_bd_instance

# Create interface ports

# Create ports
set M_ACP_ACLK [ create_bd_port -dir I -type clk M_ACP_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_ACP_ACLK
set M_ACP_ARESETN [ create_bd_port -dir I -type rst M_ACP_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_ACP_ARESETN
set M_GP0_ACLK [ create_bd_port -dir I -type clk M_GP0_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_GP0_ACLK
set M_GP0_ARESETN [ create_bd_port -dir I -type rst M_GP0_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_GP0_ARESETN
set M_GP1_ACLK [ create_bd_port -dir I -type clk M_GP1_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_GP1_ACLK
set M_GP1_ARESETN [ create_bd_port -dir I -type rst M_GP1_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_GP1_ARESETN
set M_HP0_ACLK [ create_bd_port -dir I -type clk M_HP0_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_HP0_ACLK
set M_HP0_ARESETN [ create_bd_port -dir I -type rst M_HP0_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_HP0_ARESETN
set M_HP1_ACLK [ create_bd_port -dir I -type clk M_HP1_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_HP1_ACLK
set M_HP1_ARESETN [ create_bd_port -dir I -type rst M_HP1_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_HP1_ARESETN
set M_HP2_ACLK [ create_bd_port -dir I -type clk M_HP2_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_HP2_ACLK
set M_HP2_ARESETN [ create_bd_port -dir I -type rst M_HP2_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_HP2_ARESETN
set M_HP3_ACLK [ create_bd_port -dir I -type clk M_HP3_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_M_AXI_ACLK}  ] $M_HP3_ACLK
set M_HP3_ARESETN [ create_bd_port -dir I -type rst M_HP3_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $M_HP3_ARESETN
set PS_SRSTB [ create_bd_port -dir I -from 0 -to 0 PS_SRSTB ]
set PS_CLK [ create_bd_port -dir I -from 0 -to 0 PS_CLK ]
set PS_PORB [ create_bd_port -dir I -from 0 -to 0 PS_PORB ]
set S_GP0_ACLK [ create_bd_port -dir I -type clk S_GP0_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_S_AXI_ACLK}  ] $S_GP0_ACLK
set S_GP0_ARESETN [ create_bd_port -dir I -type rst S_GP0_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $S_GP0_ARESETN
set S_GP1_ACLK [ create_bd_port -dir I -type clk S_GP1_ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0} CONFIG.CLK_DOMAIN {zynq_system_S_AXI_ACLK}  ] $S_GP1_ACLK
set S_GP1_ARESETN [ create_bd_port -dir I -type rst S_GP1_ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW}  ] $S_GP1_ARESETN

# Create instance: zynq_bfm, and set properties
set zynq_bfm [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7_bfm:2.0 zynq_bfm ]
set_property -dict [ list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.PCW_USE_M_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {1} CONFIG.PCW_USE_S_AXI_ACP {1} CONFIG.PCW_USE_S_AXI_HP0 {1} CONFIG.PCW_USE_S_AXI_HP1 {1} CONFIG.PCW_USE_S_AXI_HP2 {1} CONFIG.PCW_USE_S_AXI_HP3 {1}  ] $zynq_bfm

# Create instance: acp_master, and set properties
set acp_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 acp_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {3} CONFIG.C_M_AXI3_DATA_WIDTH {64}  ] $acp_master

# Create instance: gp0_master, and set properties
set gp0_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 gp0_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6}  ] $gp0_master

# Create instance: gp1_master, and set properties
set gp1_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 gp1_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6}  ] $gp1_master

# Create instance: hp0_master, and set properties
set hp0_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 hp0_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6} CONFIG.C_INTERCONNECT_M_AXI3_READ_ISSUING {32}  ] $hp0_master

# Create instance: hp1_master, and set properties
set hp1_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 hp1_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6} CONFIG.C_INTERCONNECT_M_AXI3_READ_ISSUING {32}  ] $hp1_master

# Create instance: hp2_master, and set properties
set hp2_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 hp2_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6} CONFIG.C_INTERCONNECT_M_AXI3_READ_ISSUING {32}  ] $hp2_master

# Create instance: hp3_master, and set properties
set hp3_master [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 hp3_master ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_M_AXI3_ID_WIDTH {6} CONFIG.C_INTERCONNECT_M_AXI3_READ_ISSUING {32}  ] $hp3_master

# Create instance: gp0_slave, and set properties
set gp0_slave [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 gp0_slave ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI3_ID_WIDTH {12} CONFIG.C_S_AXI3_BASEADDR {0x40000000} CONFIG.C_S_AXI3_HIGHADDR {0x7FFFFFFF} CONFIG.C_S_AXI3_EXCLUSIVE_ACCESS {1}  ] $gp0_slave

# Create instance: gp1_slave, and set properties
set gp1_slave [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm:5.0 gp1_slave ]
set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {0} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI3_ID_WIDTH {12} CONFIG.C_S_AXI3_BASEADDR {0x80000000} CONFIG.C_S_AXI3_HIGHADDR {0xBFFFFFFF} CONFIG.C_S_AXI3_EXCLUSIVE_ACCESS {1}  ] $gp1_slave

# Create interface connections
connect_bd_intf_net -intf_net acp_master_m_axi3 [get_bd_intf_pins acp_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_ACP]
connect_bd_intf_net -intf_net gp0_master_m_axi3 [get_bd_intf_pins gp0_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_GP0]
connect_bd_intf_net -intf_net gp1_master_m_axi3 [get_bd_intf_pins gp1_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_GP1]
connect_bd_intf_net -intf_net hp0_master_m_axi3 [get_bd_intf_pins hp0_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_HP0]
connect_bd_intf_net -intf_net hp1_master_m_axi3 [get_bd_intf_pins hp1_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_HP1]
connect_bd_intf_net -intf_net cdn_axi_bfm_1_m_axi3 [get_bd_intf_pins hp2_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_HP2]
connect_bd_intf_net -intf_net hp3_master_m_axi3 [get_bd_intf_pins hp3_master/m_axi3] [get_bd_intf_pins zynq_bfm/S_AXI_HP3]
connect_bd_intf_net -intf_net zynq_bfm_m_axi_gp0 [get_bd_intf_pins gp0_slave/s_axi3] [get_bd_intf_pins zynq_bfm/M_AXI_GP0]
connect_bd_intf_net -intf_net zynq_bfm_m_axi_gp1 [get_bd_intf_pins gp1_slave/s_axi3] [get_bd_intf_pins zynq_bfm/M_AXI_GP1]

# Create port connections
connect_bd_net -net m_axi_aclk_1 [get_bd_ports M_ACP_ACLK] [get_bd_pins acp_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_ACP_ACLK]
connect_bd_net -net m_axi_aresetn_1 [get_bd_ports M_ACP_ARESETN] [get_bd_pins acp_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_2 [get_bd_ports M_GP0_ACLK] [get_bd_pins gp0_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_GP0_ACLK]
connect_bd_net -net m_axi_aresetn_2 [get_bd_ports M_GP0_ARESETN] [get_bd_pins gp0_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_3 [get_bd_ports M_GP1_ACLK] [get_bd_pins gp1_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_GP1_ACLK]
connect_bd_net -net m_axi_aresetn_3 [get_bd_ports M_GP1_ARESETN] [get_bd_pins gp1_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_4 [get_bd_ports M_HP0_ACLK] [get_bd_pins hp0_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_HP0_ACLK]
connect_bd_net -net m_axi_aresetn_4 [get_bd_ports M_HP0_ARESETN] [get_bd_pins hp0_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_5 [get_bd_ports M_HP1_ACLK] [get_bd_pins hp1_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_HP1_ACLK]
connect_bd_net -net m_axi_aresetn_5 [get_bd_ports M_HP1_ARESETN] [get_bd_pins hp1_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_6 [get_bd_ports M_HP2_ACLK] [get_bd_pins hp2_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_HP2_ACLK]
connect_bd_net -net m_axi_aresetn_6 [get_bd_ports M_HP2_ARESETN] [get_bd_pins hp2_master/M_AXI_ARESETN]
connect_bd_net -net m_axi_aclk_7 [get_bd_ports M_HP3_ACLK] [get_bd_pins hp3_master/M_AXI_ACLK] [get_bd_pins zynq_bfm/S_AXI_HP3_ACLK]
connect_bd_net -net m_axi_aresetn_7 [get_bd_ports M_HP3_ARESETN] [get_bd_pins hp3_master/M_AXI_ARESETN]
connect_bd_net -net ps_srstb_1 [get_bd_ports PS_SRSTB] [get_bd_pins zynq_bfm/PS_SRSTB]
connect_bd_net -net ps_clk_1 [get_bd_ports PS_CLK] [get_bd_pins zynq_bfm/PS_CLK]
connect_bd_net -net ps_porb_1 [get_bd_ports PS_PORB] [get_bd_pins zynq_bfm/PS_PORB]
connect_bd_net -net s_axi_aclk_1 [get_bd_ports S_GP0_ACLK] [get_bd_pins gp0_slave/S_AXI_ACLK] [get_bd_pins zynq_bfm/M_AXI_GP0_ACLK]
connect_bd_net -net s_axi_aresetn_1 [get_bd_ports S_GP0_ARESETN] [get_bd_pins gp0_slave/S_AXI_ARESETN]
connect_bd_net -net s_axi_aclk_2 [get_bd_ports S_GP1_ACLK] [get_bd_pins gp1_slave/S_AXI_ACLK] [get_bd_pins zynq_bfm/M_AXI_GP1_ACLK]
connect_bd_net -net s_axi_aresetn_2 [get_bd_ports S_GP1_ARESETN] [get_bd_pins gp1_slave/S_AXI_ARESETN]

add_files -fileset sim_1 imports/zynq_example/run/preload_ddr.txt
add_files -fileset sim_1 imports/zynq_example/run/wr_gp0.txt      
add_files -fileset sim_1 imports/zynq_example/run/write_from_hp0.txt
import_files imports/zynq_example
set_property is_enabled false [get_files  zynqbfmsystem/zynq_system.srcs/sources_1/imports/zynq_example/tests/test_mp.v]
set_property is_enabled false [get_files  zynqbfmsystem/zynq_system.srcs/sources_1/imports/zynq_example/tests/test_regmap.v]
set_property is_enabled false [get_files  zynqbfmsystem/zynq_system.srcs/sources_1/imports/zynq_example/tests/test_mem_upd.v]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
launch_xsim -simset sim_1 -mode behavioral
run all
#close_sim
# Create address segments