* 16-bit HCS12 core
          o HCS12 CPU
          o Upward compatible with M68HC11 instruction set
          o Interrupt stacking and programmer’s model identical to M68HC11
          o Instruction queue
          o Enhanced indexed addressing
          o Memory map and interface (MMC)
          o Interrupt control (INT)
          o Background debug mode (BDM)
          o Enhanced debug12 module, including breakpoints and change-of-flow trace buffer (DBG)
          o Multiplexed expansion bus interface (MEBI) — available only in 112-pin package version
    * Wakeup interrupt inputs
          o Up to 21 port bits available for wakeup interrupt function with digital filtering
    * Memory
          o 64K bytes of FLASH EEPROM
          o 8K bytes of RAM
    * Analog-to-digital converter (ATD)
    * Serial interfaces
          o Two asynchronous serial communications interface (SCI)
          o One synchronous serial peripheral interface (SPI)
          o One inter-IC bus (IIC)
    * Ethernet Media access controller (EMAC)
          o IEEE 802.3 compliant
          o Medium-independent interface (MII)
          o Full-duplex and half-duplex modes
          o Flow control using pause frames
          o MII management function
          o Address recognition
          o Frames with broadcast address are always accepted or always rejected
          o Exact match for single 48-bit individual (unicast) address
          o Hash (64-bit hash) check of group (multicast) addresses
          o Promiscuous mode
    * Ethertype filter
    * Loopback mode
    * Two receive and one transmit Ethernet buffer interfaces
    * Ethernet 10/100 Mbps transceiver (EPHY)
    * 80-pin TQFP-EP or 112-pin LQFP package

    * High-performance 16-bit HCS12 CPU core
          o Upward compatible with M68HC11 instruction set
          o Interrupt stacking and programmer's model identical to M68HC11
          o Instruction pipe
          o Enhanced indexed addressing
          o Multiplexed external bus
    * Maximum 30MHz bus operation at 5V
    * Memory
          o 32K byte Flash EEPROM
          o 3.5K byte RAM
    * Up to 75 input/output (I/O) lines
    * Integrated Queue controller (IQUE)
    * 8-channel, 16-bit enhanced capture timer
    * Full/High speed universal serial bus 2.0 (USB 2.0)
    * Serial communications interface (SCI)
    * ATA-5 host controller interface
    * Flash memory card interfaces
          o Compact Flash host controller
          o Secure digital/multimedia card host controller
          o Smartmedia host controller
          o Memory stick host controller
    * Available in 100-pin LQFP package. 64-pin LQFP planned for Q3 2004