setbit(ad_cs_port,ad_cs_pin);    //CS->1(desable)
   clrbit(ad_res_port,ad_res_pin); //RES->0
   delay_ms(100);
   setbit(ad_res_port,ad_res_pin);  //RES->1
   delay_ms(100);
   //------------
   write_ad(0x20); /* Active Channel is Ain1(+)/Ain1(.), next operation as write to the clock register */
   write_ad(0x07);  /* master clock enabled, 2.4576 MHz Clock, set output rate to 500Hz*/
   write_ad(0x10); /* Active Channel is Ain1(+)/Ain1(.), next operation as write to the setup register */
   write_ad(0x44); /* gain = 1, unipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/

int main(void) {
    TCCR1A = _BV(COM1B0);  //Togle OC1B on compare match
    TCCR1B = _BV(WGM12) | _BV(CS11);  //div=8, CTC mode

    OCR1B = 0x07d0; //1 kHz -> GCLK

    PORTB = 0x00;
    DDRB = 0b11010111;  // XXX GCLK XXX XXX SDO SDI DCLK LE

    PORTB |= _BV(PB2); // SDI

    sei();

    for (uint8_t j=0;j<16;j++) {
        for (uint8_t i=0;i<16;i++) {
            if (((i==15) && (j<15)) || ((i==13) && (j>14))) {
                PORTB |= _BV(PB0);  // LE -> 1
            }
            PORTB &= ~_BV(PB1);  // DCLK -> 0
            _delay_us(50);    
            PORTB |= _BV(PB1);  // DCLK -> 1
            _delay_us(50);
            if (i==15) {
                PORTB &= ~_BV(PB0); // LE -> 0
            }
        }
        PORTB &= ~_BV(PB1); // DCLK -> 0
        _delay_us(50);  // Пауза между каждым выводом
    }    
    while (1) {
    }
}

Display technique: 1/8 duty 1/4 bias drive (5 ´ 7 dots)
                            1/9 duty 1/4 bias drive (5 ´ 8 dots)
                          1/10 duty 1/4 bias drive (5 ´ 9 dots)